Juntran Technologies - Design for Testability Engineer (3-5 yrs)

Role Summary :

We are seeking a skilled Design for Testability (DFT) Engineer to join our VLSI design team.

The candidate will be responsible for developing and implementing DFT strategies to enhance test coverage, reduce costs, and ensure the manufacturability of high-quality semiconductor devices.

We are hiring B.Tech 2021, 2022 trained freshers who are passionate about VLSI design and eager to build a career in the semiconductor industry.

Key Responsibilities :

- Develop and implement DFT architectures such as scan, BIST, boundary scan, and MBIST.

- Work closely with design teams to integrate DFT features into RTL and gate-level designs.

- Perform ATPG, fault grading, and analyze test coverage.

- Collaborate with verification teams for validating DFT implementations.

- Support ATE test program development and debugging.

Required Skills :

- Proficiency in DFT methodologies and tools (e.g, Mentor Tessent, Synopsys DFTMAX, Cadence Modus).

- Hands-on experience with ATPG, fault simulation, and scan insertion.

- Knowledge of RTL design and verification.

- Familiarity with scripting languages (Python, Perl, Tcl) for automation.

- Understanding of semiconductor manufacturing processes.

- Strong analytical and problem-solving skills.

- Ability to work collaboratively in a team-oriented environment