Juntran Technologies - RTL Design Engineer (3-5 yrs)

Role Summary :

We are looking for an RTL Design Engineer to develop and implement high-performance digital designs from specification to synthesis-ready RTL.

We are hiring B.Tech 2021, 2022 trained freshers who are enthusiastic about digital design and ready to contribute to cutting-edge projects.

Key Responsibilities :

- Develop RTL designs based on specifications and requirements.

- Perform micro-architecture design and write high-quality RTL code.

- Collaborate with verification teams to ensure thorough validation.

- Conduct synthesis and timing analysis to ensure design meets performance targets.

- Support integration of RTL designs into the SoC environment.

- Identify and resolve design bottlenecks during implementation.

Required Skills :

- Proficiency in hardware description languages (Verilog, SystemVerilog, VHDL).

- Strong understanding of digital design fundamentals (FSMs, pipelines, clock domains).

- Experience with EDA tools for synthesis and timing analysis (Synopsys DC, Cadence Genus).

- Familiarity with low-power design methodologies.

- Knowledge of scripting languages (Python, Tcl, Perl) for automation.

- Strong interpersonal and communication skills