Lead Design Engineer

• The responsibility primarily entails performing pre and post silicon Physical Layer Electrical Validation on Cadences High Speed SERDES IP.

Activities include

• Designing the hardware and software infrastructure required to enable validation (Test PCBs, Controlling FPGA platforms, Labview/Python automation)
• Implementing test suites for rigorously testing the compliance of the IP to Physical Layer Electrical specifications
• Debugging Silicon issues and generating high quality test reports for customers

Minimum Qualifications:

• BE/BTECH/ME/MTECH Equivalent Degree
• 3-4 years (with Btech) or 1-2 years (with Mtech) of experience in Post-Silicon Physical Layer Electrical Validation
• Physical Layer electrical validation experience on AT LEAST ONE High speed SERDES protocol like PCIe, USB, DP, Ethernet, SRIO, JESD204, DDRIO
• Hands on Experience in using lab equipment such as Oscilloscopes, Network Analyzers, Bit Error Rate Testers (BERT)