Principal Verification Engineer

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique One Cadence - One Team culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day.

Job Summary:

• We are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in Emulation domain. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other s success, and are passionate about technology and innovation.

Position Description:

• Product validation engineer to work on key Palladium technologies including UPF. Position is based in Noida/Bangalore.
• Role involves verification of various upcoming features in Palladium.
• Work also involves managing current set of regressions.
• Participate in technical discussions, including Functional Specification reviews, Testplan reviews etc
• Review and guide team members on technical deliverables from the team
• Person will be fully responsible and accountable for quality of releases and features for Palladium emulation technology.
• Mentor juniors in the team
• Contribute towards the improvement of existing emulation validation/verification flows

Position Requirements:

• The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).
• Prior experience in Emulation/UPF will be big plus. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) specially Palladium with focus towards debugging design/ verification problems.
• Experience in process automation with scripting.
• Experience with SystemVerilog, C++, UVM.
• Experience with Functional Verification of complex digital systems, e. g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.

Behavioral skills required:

• Must possess strong written, verbal and presentation skills.
• Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what s possible to get the job done, including creative use of unconventional solutions
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity