Mempage Technologies - Soc Verification Engineer - System Verilog (3-10 yrs)

Key Responsibilities :

- Develop and implement test plans for SoC verification, focusing on both block-level and full-chip environments.

- Create and maintain UVM-based test benches for the verification of complex digital designs.

- Perform UPF-based verification for power-aware SoC designs, ensuring power management features function correctly across various scenarios.

- Work closely with design, architecture, and software teams to debug and resolve verification issues.

- Develop and execute test scenarios to verify functionality, performance, and power requirements of the SoC.

- Automate verification tasks to improve coverage and efficiency, utilizing scripting languages such as Python, Perl, or TCL.

- Analyze and document verification results, and provide feedback and suggestions for design improvements.

- Participate in code reviews and contribute to the enhancement of verification methodologies and processes.

- Collaborate with cross-functional teams to define verification goals, milestones, and deliverables.

Required Qualifications :

- 3-10 years of experience in SoC verification, with a strong focus on UVM methodology.

- Hands-on experience with UPF (Unified Power Format) for power-aware verification.

- Proficiency in hardware description languages such as SystemVerilog and VHDL.

- Strong understanding of digital design and verification concepts, including clock domains, reset strategies, and low-power design.

- Experience with simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Graphics Questa) and waveform viewers.

- Familiarity with scripting languages (Python, Perl, TCL) for automation and verification flow improvements.