Soc Verification Engineer Interview Questions and Answers

UVM has 4 phases: build, connect, run, and cleanup. Reg is a hardware component, logic is a design component.

• UVM phases are build, connect, run, and cleanup

• Build phase creates the test environment

• Connect phase connects the testbench to the design

• Run phase executes the test

• Cleanup phase destroys the test environment

• Reg is a hardware component that stores data

• Logic is a design component that performs operations on data