Design Verification Engineer

The position involves designing, developing and deploying UVM based reusable testbenches for RTL unit blocks, sub-system level and top level systems with emphasis on

verifying the functionality and generating the code/functional coverage reports. The candidate should come up with test plans and test cases in order to achieve 100% code coverage and functional coverage.

Educational Qualification:

Bachelor major in electronics, embedded programming, ECE, EEE.

Key Requirements:

Experience in ASIC/FPGA verification using System Verilog.

Develop and sign off on test plans and test cases.

Strong knowledge of digital design, Verilog, System Verilog, UVM, C/C++.

Experience in AMBA AHB/AXI/APB based IPs design/verification.

Experience in usage of assertions, constrained random generation, functional and code

coverages.

Experience in FPGA design and FPGA EDA tools will be a plus.

Experience in scripting, such as TCL, Perl, Bash and python to automate the verification

methodologies and flows.

Able to build and set up scalable simulation / verification environments.

Ability to focus on finding the design issues and corner cases.

Knowledge of version control systems (GIT is preferable).

Knowledge of invoking the MATLAB DPI checker (or any foreign language) in the UVM

scoreboard is more advantageous (Basic knowledge in MATLAB also a plus