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SR Electro LLP
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I applied via Naukri.com and was interviewed in Dec 2022. There were 2 interview rounds.
Object-oriented concepts and design involve creating classes and objects that encapsulate data and behavior.
Object-oriented programming is based on the principles of encapsulation, inheritance, and polymorphism.
Classes are used to define objects, which contain data and methods that operate on that data.
Inheritance allows classes to inherit properties and methods from other classes, while polymorphism allows objects to ...
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posted on 14 Jan 2022
I applied via Referral and was interviewed before Jan 2021. There were 3 interview rounds.
I applied via Referral and was interviewed before Mar 2020. There were 3 interview rounds.
posted on 13 Jan 2024
I applied via Referral and was interviewed before Jan 2023. There were 2 interview rounds.
Ap per your job profile
posted on 11 Jun 2022
PPAP documents are developed in the Production Part Approval Process (PPAP) face.
PPAP documents are developed during the production part approval process.
This is typically the fourth phase of the APQP (Advanced Product Quality Planning) process.
PPAP documents include items such as control plans, FMEAs, and measurement system analysis.
The purpose of PPAP is to ensure that all parts meet customer requirements and specifi...
The shrinkage value of pa66 varies depending on the specific grade and processing conditions.
Shrinkage is the reduction in size of a molded part as it cools and solidifies.
The shrinkage value of pa66 can range from 1.5% to 3.5%.
Factors that affect shrinkage include mold design, processing parameters, and part geometry.
It is important to account for shrinkage when designing molds and parts to ensure proper fit and funct
I applied via Naukri.com and was interviewed before Aug 2021. There were 2 interview rounds.
I applied via Campus Placement and was interviewed before Oct 2022. There were 3 interview rounds.
UVM is a methodology for verifying complex designs using SystemVerilog. Blocking assignments execute sequentially, while non-blocking assignments execute concurrently.
UVM (Universal Verification Methodology) is a standardized methodology for verifying complex designs in SystemVerilog.
Blocking assignments in SystemVerilog execute sequentially, meaning the next statement waits for the current statement to finish.
Non-bloc...
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R&D Engineer
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