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I applied via LinkedIn and was interviewed in Jul 2024. There was 1 interview round.
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I applied via Campus Placement and was interviewed in Aug 2024. There were 3 interview rounds.
Aotitude,core que on all subjects in ece
I completed a 6-month internship at XYZ Company where I gained hands-on experience in physical design tools and methodologies.
Worked on floorplanning, placement, and routing of digital designs
Utilized tools such as Cadence Innovus and Synopsys ICC
Collaborated with cross-functional teams to optimize design performance
Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.
Occurs when signals from one trace interfere with signals on another trace
Can lead to signal distortion or errors in data transmission
Prevented by proper spacing and shielding between traces
Example: Cross talk between data lines on a PCB causing errors in communication
Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.
Specify the source clock for the generated clock
Define the edge (rising/falling) on which the generated clock is based
Use tools like Synopsys Design Compiler to define generated clocks
I applied via LinkedIn and was interviewed in Jul 2023. There were 2 interview rounds.
Floorplan strategies involve calculating maximum macro counts, considering placement constraints and addressing congestion issues.
Floorplan strategies involve determining the maximum number of macros that can be accommodated within a block.
Placement constraints refer to the rules and guidelines that dictate where macros can be placed within the block.
Congestion issues arise when there is limited space or resources avai...
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
posted on 10 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There were 2 interview rounds.
Mcq questions based on aptitude(a bit ) and digital design, VLSI, Clock related questions
posted on 5 Apr 2024
I applied via Recruitment Consulltant and was interviewed in Sep 2023. There was 1 interview round.
The temperature of the design I worked on was optimized to ensure proper functionality and reliability.
The temperature was carefully controlled to prevent overheating and ensure performance.
Thermal analysis was conducted to determine the optimal operating temperature.
Cooling solutions such as heat sinks or fans were implemented to manage heat dissipation.
Examples: The design operated within a temperature range of 0-70 ...
Interview experience
Staff Engineer
5
salaries
| ₹35 L/yr - ₹43.7 L/yr |
Software Engineer
4
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| ₹15 L/yr - ₹32 L/yr |
Senior Engineer
4
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Senior Application Engineer
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Design Engineer
3
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Texas Instruments
Analog Devices
Infineon Technologies
STMicroelectronics