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I applied via Approached by Company and was interviewed in May 2022. There were 3 interview rounds.
I applied via Referral and was interviewed before Sep 2023. There were 2 interview rounds.
Criticality in projects refers to the importance of certain tasks or components in achieving project goals.
Identify critical tasks that have a high impact on project success
Allocate resources and prioritize critical tasks to ensure timely completion
Regularly monitor and assess progress of critical tasks to mitigate risks
Examples: Timing closure in ASIC design, power optimization in SOC design
I applied via Referral and was interviewed before May 2023. There was 1 interview round.
Design a clock signal with a frequency 13 times higher than the input signal.
Multiply the input clock frequency by 13 to get the desired output frequency.
Use a PLL (Phase-Locked Loop) to generate the higher frequency clock signal.
Ensure the clock signal meets timing requirements for the design.
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I was interviewed before Nov 2021.
Intel interview questions for designations
I was interviewed before Sep 2016.
I was interviewed before Sep 2016.
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
posted on 24 Sep 2024
I applied via campus placement at Amrita Vishwa Vidyapeetham, Amritapuri Campus and was interviewed in Aug 2024. There were 4 interview rounds.
Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.
Occurs when signals from one trace interfere with signals on another trace
Can lead to signal distortion or errors in data transmission
Prevented by proper spacing and shielding between traces
Example: Cross talk between data lines on a PCB causing errors in communication
Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.
Specify the source clock for the generated clock
Define the edge (rising/falling) on which the generated clock is based
Use tools like Synopsys Design Compiler to define generated clocks
2 Interview rounds
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