GPU SOC Design Engineer

Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies, drives unit level verification, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the GPU block.Additional Details::

• You will be responsible for designing and/or integrating IP for a discrete graphics SoC. You will be working or assisting in architecture, design, implementation, formal verification, emulation and validation of discrete graphics SoC products, including:
• Creating a design to produce key assets that help improve product KPIs for discrete graphics products.
• Working with SoC Architecture and platform architecture teams to establish silicon requirements.
• Making appropriate design trade off balancing risk, area, power, performance, validation complexity and schedule.
• Creating micro architectural specification document for the design.
• Working with external vendors on tools or IPs required for the development of micro-architecture, design and design qualification of custom silicon designs.
• Driving vendor's methodology to meet world class silicon design standards.
• Architecting area and power efficient low latency designs with scalabilities and flexibilities.
• Power and Area efficient RTL logic design and DV support.
• Running tools to ensure lint-free and CDC/RDC clean design, VCLP.
• Synthesis and timing constraints.

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• BS+8 Years of relevant industry experience.
• Having achieved multiple tape-outs reaching production with first pass silicon.
• Ability to drive and improve digital design methodology to achieve high quality first silicon.
• Hands on experience with FPGA emulation, silicon bring-up, characterization and debug.
• Able to work with multi-functional teams within Intel and external vendors across geographical boundaries to resolve architectural and implementation challenges with a focus on schedule.
• Strong verbal and written communication skills.
• Good understanding of verilog and system verilog, synthesizable RTL.
• Knowledgeable in modern design techniques and energy-efficient/low power logic design and power analysis.
• Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.