Design Verification Engineer

Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications.

Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment.

Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features.

Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology.

Absorbs learning from post silicon on the quality of validation done during micro architects development, updates test plan for missing coverages, and proliferates to future products.

Minimum Qualifications:

• BS with 10+ years/MS with 8+ years industry experiences
• Experience on Pre-Si validation on Emulation, preferably Zebu.
• Experience on validation at MCP.
• Experience with pre-Si verification with System Verilog OVM/UVM on content development Scripting languages such as Python, Simics.
• Good understanding of RTL, Verilog, VHDL.

Preferred Qualifications:

• Experience with Synopsys simulation and coverage tools.
• Assertion based verification
• Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.