The Client Development Group (CDG) is looking for a highly motivated SOC/IP RTL Design Engineer Lead to join the client SOC frontend design and integration team for the next generation of Client SOC.
In this role, the candidate's responsibilities include, although not limited to:
Understand IP and SOC arch/urach requirements for building client SOC, understand the global flows like clock, power delivery, design for debug (DFD) etcFamiliar with IP/SOC design tools, flows and methodology.
Familiar with all aspects of the SoC/IP design flow from high-level design to synthesis, timing and power to create a design database that is ready for manufacturing.
Have thorough understanding of design quality requirements for delivering a robust and scalable IP.
Perform integration of functional units and subsystems into SoC full chip.
Have good understanding of uarch concepts and RTL coding .
Run, analyse and fix various quality check tools and flows such as CDC, lint, VCLP, etc.
Define power domains using UPF and hit performance, power and area targets.
Work with backend engineers on pre and post physical design timing closure.
Work with verification engineering to debug test cases in RTL and Gate Level simulation environment.
Work with cross-functional teams to make sure designs are delivered on time, and with highest quality, by incorporating proper checks at every stage of the design process.
As a lead, set priorities for the team, get results across boundaries, ensure an inclusive work environment, develop employees.
Qualifications
Bachelor's in Electrical/ Computer Engineering, Computer Science or related field plus 8+ years of relevant experience. OR a Master's degree in Electrical/Computer Engineering, Computer Science or related field with 6+years of relevant experience. ( Years of Experience updated)