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Broadcom Dft Design Engineer Interview Questions, Process, and Tips for Experienced
Broadcom Dft Design Engineer Interview Experiences for Experienced
1 interview found
Anonymous
I applied via Referral and was interviewed in Jun 2022. There was 1 interview round.
(6 Questions)
- Q1. 1st round with hiring manager.Discussion with hiring manager. Reason for switch. Then technical questions on how to debug and find failure flops in a chain. Basic loc,los, loes lock-up latch questions. Why...
- Q2. 3 2 hour interviews were taken( Total 6 hours with 1 people in each round). Questions: how we can reduce test time. how serial chain patterns are solved. How T24 violations are debugged, how we can find wh...
- Q3. How compression ratio can be tweaked, what are the factors ( how coverage, Patten count gets impacted).
- Ans.
Compression ratio can be tweaked by adjusting the volume of the combustion chamber. This affects fuel efficiency and power output.
Compression ratio is the ratio of the volume of the combustion chamber at its largest to its smallest.
Increasing compression ratio can improve fuel efficiency and power output, but too high a ratio can cause engine knocking.
Factors that impact compression ratio include the size and shape of ...
- Q4. How have I observed hold violations and setup violations in my design. What I did after that, etc
- Ans.
I have observed hold and setup violations in my design and took necessary actions.
I used static timing analysis (STA) to identify hold and setup violations.
I fixed hold violations by adding delay cells or increasing clock period.
I fixed setup violations by reducing delay or decreasing clock period.
I also checked for false paths and multi-cycle paths.
I re-ran STA after fixing violations to ensure timing closure.
I docume...
- Q5. Purpose of occ controllers. What scan enable signals( pipelined or nonpiplelined) will go to my occ controller, clock chain and why. Lock up latch purpose. If I have 5 negative edge triggered flops and 5 p...
- Ans.
Explanation of purpose of occ controllers, scan enable signals, lock up latch and arrangement of negative and positive edge triggered flops.
The purpose of occ controllers is to manage the clock signals in a design and ensure proper timing.
Scan enable signals are used for testing and debugging purposes.
Pipelined signals are used for faster data transfer while non-pipelined signals are used for simpler designs.
Lock up la...
- Q6. How can we reset a tap controller without trst signals. How do you find coverage gaps.
- Ans.
Resetting a tap controller without trst signals and finding coverage gaps.
For resetting a tap controller without trst signals, we can use a power-on reset circuit or a watchdog timer.
To find coverage gaps, we can use code coverage analysis tools like CodeSonar, Coverity, or LDRA.
We can also use dynamic analysis tools like Valgrind or Purify to find runtime errors and coverage gaps.
Manual testing and peer code reviews c...
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I applied via Referral and was interviewed before Jan 2021. There were 5 interview rounds.
Interview Questionnaire
2 Questions
- Q1. Basic data structures questions from bit manipulation, trees, arrays, string
- Q2. Questions related to previous company work.
Interview Preparation Tips
Selected
I applied via Company Website and was interviewed before Oct 2022. There were 2 interview rounds.
(4 Questions)
- Q1. 3-4 rounds of c and DSP questions.
- Q2. Fourier transform
- Q3. Digital filtering
- Q4. C coding and basics
Interview Preparation Tips
Selected
I applied via Qualcomm Careers and was interviewed in Dec 2023. There were 4 interview rounds.
(1 Question)
- Q1. Managerial Introduction and alignment with the job role.
(1 Question)
- Q1. Technical Hardware Questions
(1 Question)
- Q1. Technical Software/Scripting Questions
(1 Question)
- Q1. General HR discussions
Interview Preparation Tips
Selected
I applied via Qualcomm Careers and was interviewed in Dec 2023. There were 4 interview rounds.
(1 Question)
- Q1. Managerial Introduction and alignment with the job role.
(1 Question)
- Q1. Technical Hardware Questions
(1 Question)
- Q1. Technical Software/Scripting Questions
(1 Question)
- Q1. General HR discussions
Interview Preparation Tips
Selected
I appeared for an interview before Feb 2023.
Practice on hackerrank, they send hackerrank link for screening round.
(1 Question)
- Q1. C, os, embedded questions
(1 Question)
- Q1. C, data structures,os
(1 Question)
- Q1. Previous jobs, salary discussion, relocation
Interview Preparation Tips
Gaurav Kumar
Selected
I applied via Referral and was interviewed in Sep 2023. There were 4 interview rounds.
(2 Questions)
- Q1. Find the length of longest common subsequence in given strings.
- Ans.
The length of the longest common subsequence in given strings is found using dynamic programming.
Use dynamic programming to find the length of the longest common subsequence.
Compare characters of the strings and build a matrix to store the lengths of common subsequences.
Traverse the matrix to find the length of the longest common subsequence.
- Q2. A basic DFS based graph question.
Write the algorithm for topological sorting.
(2 Questions)
- Q1. Basic system design questions.
- Q2. Explain CAP theorem.
- Ans.
CAP theorem states that in a distributed system, it is impossible to simultaneously guarantee consistency, availability, and partition tolerance.
Consistency: All nodes in the system have the same data at the same time.
Availability: Every request gets a response, even if some nodes are down.
Partition Tolerance: The system continues to operate despite network partitions.
In a distributed system, you can only achieve two o...
(1 Question)
- Q1. Explain your previous projects .
Skills evaluated in this interview
(2 Questions)
- Q1. What is VLSI design cycle ?
- Ans.
VLSI design cycle is the process of creating integrated circuits by going through various stages from design to fabrication.
VLSI design cycle involves stages like specification, design, verification, synthesis, and fabrication.
It starts with defining the requirements and specifications of the integrated circuit.
Design phase includes logic design, circuit design, and physical design.
Verification ensures that the design ...
- Q2. FIFO Pipeline depth calculation
(1 Question)
- Q1. Verilog code debug question
Interview Preparation Tips
Skills evaluated in this interview
I applied via Approached by Company and was interviewed in Feb 2022. There was 1 interview round.
(1 Question)
- Q1. Modem related like Tx power LNA camping issues debug Few data scenarios
Interview Preparation Tips
I applied via Naukri.com and was interviewed in Sep 2021. There were 3 interview rounds.
Interview Questionnaire
2 Questions
- Q1. String Reversal
- Q2. Bit manipulation
Interview Preparation Tips
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