Filter interviews by
Clear (1)
I applied via Referral and was interviewed before May 2023. There was 1 interview round.
Broadcom is a global technology company that designs, develops, and supplies semiconductor and infrastructure software solutions.
Broadcom is headquartered in San Jose, California.
The company was founded in 1991.
Broadcom's products are used in various industries, including networking, storage, broadband, wireless, and industrial.
Some of Broadcom's notable products include Wi-Fi chips, Bluetooth chips, and Ethernet switc...
Broadcom is a leading technology company with a strong reputation for innovation and growth.
Broadcom has a diverse portfolio of products and services that align with my interests and skills.
Broadcom has a strong track record of success and growth, which provides opportunities for career advancement.
Broadcom values its employees and fosters a culture of collaboration and innovation.
Broadcom is a leader in the industry a...
Planning to pursue a master's degree in engineering.
Researching universities with strong engineering programs
Preparing for standardized tests like GRE
Networking with alumni and professionals in the field
Applying for scholarships and financial aid
Considering online or part-time programs for flexibility
Broadcom interview questions for designations
Top trending discussions
I applied via Campus Placement and was interviewed in Dec 2016. There were 4 interview rounds.
A 2 to 1 mux can be designed using logic gates or multiplexer ICs.
A 2 to 1 mux has 2 inputs and 1 output.
It selects one of the inputs based on the value of the select input.
The truth table for a 2 to 1 mux can be used to design the circuit.
Multiplexer ICs like 74HC153 can be used to implement the design.
The output of the mux can be connected to a logic gate or another mux for further processing.
I was interviewed before Jun 2016.
Moore state model outputs depend only on the current state, while Mealy state model outputs depend on both current state and inputs.
Moore model: output is a function of current state only
Mealy model: output is a function of current state and inputs
Moore model has a separate output function, while Mealy model combines output and state transition functions
Example: vending machine can be modeled using Mealy model as outpu...
State diagram and clocked D-flipflop circuit for a 0110 sequence detector.
The state diagram will have four states: S0, S1, S2, and S3.
The circuit will have four D-flipflops, one for each state.
The output of the circuit will be high when the sequence 0110 is detected.
The clock signal will be used to synchronize the flipflops.
The state diagram and circuit can be designed using software like Quartus or Xilinx.
Parity is a method of error detection in digital communication. It involves adding an extra bit to a data stream to ensure even or odd number of 1s.
Parity is used to detect errors in data transmission.
It involves adding a parity bit to a data stream.
The parity bit is set to 1 or 0 depending on whether the number of 1s in the data stream is even or odd.
If an error occurs during transmission, the parity bit will be incor...
Designing a memory organization based on size and block units.
Determine the size of the memory and the size of each block unit
Choose a suitable memory organization scheme such as direct mapping, associative mapping, or set-associative mapping
Implement the chosen scheme and test for efficiency and accuracy
A random number generator circuit diagram can be created using a noise source and an amplifier.
Use a noise source such as a Zener diode or a reverse-biased transistor
Amplify the noise signal using an amplifier circuit
Use a comparator to convert the analog signal to a digital signal
Add a clock circuit to control the output frequency
A Schmitt trigger/inverter is a circuit that converts a noisy input signal into a clean digital output signal.
It has two threshold voltage levels: a high threshold and a low threshold
The output of the circuit changes state only when the input voltage crosses one of the threshold levels
It is commonly used in digital circuits to clean up noisy signals and to provide hysteresis
Examples include debouncing switches, signal
To optimize power usage/delay in AND gates, arrange inputs based on their capacitance and resistance.
Arrange inputs with lower capacitance and resistance closer to the gate
Inputs with higher capacitance and resistance should be placed farther away
Consider the layout of the circuit and the routing of the wires
Simulation tools can be used to determine optimal input arrangement
Answering a question on drawing CMOS circuit and W/L sizing for a given logic equation.
Understand the logic equation and its truth table
Use CMOS inverter and NAND gates to implement the logic
Size the transistors based on their role in the circuit
Check the circuit for correct functionality
Examples: AND gate, OR gate, XOR gate
A circuit for a set of logic equations using PLA
PLA stands for Programmable Logic Array
PLA is a type of digital circuit used to implement combinational logic circuits
The circuit consists of an AND array and an OR array
Inputs are fed into the AND array and the outputs are fed into the OR array
Example: A PLA circuit for a 2-input XOR gate would have 2 inputs, 2 AND gates, and 1 OR gate
An SRAM cell is a type of memory cell that stores a single bit of data using two cross-coupled inverters.
Consists of two inverters connected in a feedback loop
Has two stable states, representing 0 and 1
Uses two access transistors to read and write data
Commonly used in cache memory and microprocessors
Draw output waveforms for a logic circuit given delays for gates and wires.
Identify the logic gates and their delays
Determine the propagation delay for each wire
Use the delays to calculate the output waveform
Draw the waveform using a timing diagram
Min-Cut placement algorithm is used to place blocks on a given chip area.
Min-Cut algorithm partitions the chip into two parts and minimizes the cut between them
It is a graph-based algorithm that uses a flow network to represent the chip and its blocks
The algorithm iteratively partitions the network until all blocks are placed
Example: Placing logic gates on a microprocessor chip
Design a circuit to get an output of frequency f/3 from a clock waveform of frequency f.
Use a counter to divide the frequency by 3
Implement a flip-flop to toggle the output
Use logic gates to control the counter and flip-flop
My M.Tech. project was focused on developing a machine learning algorithm for predicting stock prices.
Used historical stock data to train the algorithm
Implemented various machine learning techniques such as regression and neural networks
Achieved an accuracy of 80% in predicting stock prices
Explored the impact of news articles on stock prices
Qualcomm is a multinational semiconductor and telecommunications equipment company.
Founded in 1985 in San Diego, California
Specializes in designing and manufacturing wireless telecommunications products and services
Known for their Snapdragon processors used in smartphones and other mobile devices
Also involved in developing 5G technology and Internet of Things (IoT) devices
Has partnerships with various companies includi
Yes, I have worked in groups on various projects.
I have worked in groups during my college projects.
I have also worked in groups in my previous job on a software development project.
In both cases, we had to collaborate and divide tasks among team members.
We had regular meetings to discuss progress and address any issues.
I found that working in a group allowed us to leverage each other's strengths and produce better res
Clock gating is a power-saving technique used in digital design to disable the clock signal to certain parts of a circuit when they are not in use.
Clock gating helps reduce power consumption by stopping the clock signal to unused parts of the circuit.
It is achieved by inserting logic gates in the clock signal path to control when the clock is allowed to reach certain elements.
Clock gating can be implemented at differen...
I applied via LinkedIn and was interviewed before Sep 2022. There was 1 interview round.
WLAN connection procedure involves scanning for available networks, selecting a network, entering the password, and connecting to the network.
Scan for available networks
Select a network to connect to
Enter the password for the selected network
Establish connection to the network
based on 1 interview
1 Interview rounds
Software Engineer
135
salaries
| ₹0 L/yr - ₹0 L/yr |
Senior Software Engineer
127
salaries
| ₹0 L/yr - ₹0 L/yr |
Accountant
119
salaries
| ₹0 L/yr - ₹0 L/yr |
Principal Software Engineer
50
salaries
| ₹0 L/yr - ₹0 L/yr |
Test Engineer
48
salaries
| ₹0 L/yr - ₹0 L/yr |
D E C
Fedder And Garten
Hi Technologies Limited, UAB
JK Khanna & Co.