AdeptChip Services Verification Engineer Interview Questions and Answers

Q1. Project Explanation
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Q2. Basic Array Question
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Q3. Why should I hire you
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I have a strong background in embedded systems design and development, with a proven track record of delivering high-quality solutions.
• Extensive experience in designing and implementing embedded systems for various applications

• Proficient in programming languages such as C, C++, and assembly language

• Strong problem-solving skills and ability to troubleshoot complex issues

• Excellent communication and teamwork skills, able ...read more
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Q1. Is setup and hold uncertainty values are different
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Yes, setup and hold uncertainty values are different in physical design engineering.
• Setup uncertainty is related to the arrival time of the data signal at the input of the flip-flop, while hold uncertainty is related to the removal time of the data signal.

• Setup time is the minimum amount of time the data input must be stable before the clock edge, while hold time is the minimum amount of time the data input must be sta...read more
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Q1. What is an ICG? How would you use it in the design?
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ICG stands for Inter-Chip Global. It is a network that connects multiple chips in a system.
• ICG is used to transfer data between different chips in a system

• It helps in reducing the number of wires required for communication between chips

• ICG can be used in various design aspects such as clock distribution, power management, and data transfer

• Example: In a multi-chip system, ICG can be used to transfer clock signals from o
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Q2. How will MSCTS help at SOC level CTS
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MSCTS can help in achieving better clock distribution and reducing skew at SOC level CTS.
• MSCTS (Multi-Source Clock Tree Synthesis) can optimize the clock tree for better skew and jitter performance.

• It can also help in reducing power consumption by optimizing the clock network.

• MSCTS can handle multiple clock sources and ensure proper synchronization.

• It can also help in meeting timing constraints and reducing clock tree ...read more
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Q1. What was the most difficult challenge faced in the projects you worked?
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Q2. How will you fix setup and hold time when both are violating at the same time.
Ans. 
Fixing setup and hold time violations simultaneously requires adjusting clock timing and/or data path delays.
• Identify the critical path causing the violations

• Adjust the clock timing to meet setup and hold requirements

• Adjust the data path delays to meet setup and hold requirements

• Use tools like static timing analysis and delay calculation to determine necessary adjustments

• Iteratively adjust timing and delays until viola
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Normal Aptitude questions, We can prepare for it using general aptitude questions available in internet.

Q1. Technical Questions (Digital Electronics, Verilog, Computer Architecture)
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Q1. HR Discussion will just our introduction and some normal hr questions
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Q1. Storage classes
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Q2. Coding ques on c
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Q3. Single linked list
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Mostly on TB components coding, different scenario coding..

Mostly on past project experience, different implementation on those projects.

Q1. On background details
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Q2. Reason of job change
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Seeking new challenges and growth opportunities in the field of verification engineering.
• Desire to work on more complex projects

• Opportunity to learn and apply new technologies

• Seeking a more collaborative and supportive work environment

• Career advancement and professional development

• Company restructuring or downsizing

• Relocation or commute concerns
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Q1. Write code randc behaviour
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randc behavior generates random complex numbers with specified distribution
• Use randc to generate random complex numbers

• Specify distribution using arguments like mean, variance, etc.

• Example: randc(10, 1, 2) generates 10 random complex numbers with mean 1 and variance 2
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Q2. Functinal coverage
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Q3. Code coverage related questions
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Q4. Monitor and scoreboard connections
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Q5. Project related questions
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