Upload Button Icon Add office photos
filter salariesFilter salaries by

Yoctozant Technologies Asic Design Verification Engineer salaries in India

Annual salary range
Select experience
₹10.8 Lakhs - ₹13.8 Lakhs
Low Confidence
info icon
Low confidence means that this average salary is based on data that was reported by very few people.
Salary of majority employees
unlock blur
unlock blur

Interested in this particular role?

Last Updated: 28 Oct 2024

Companies similar to Yoctozant Technologies for Asic Design Verification Engineer

Company name Avg Annual Salary Open Jobs
Logo
TCS Asic Design Verification Engineer Salary

2 - 3 years exp. (3 salaries)

unlock blur

₹3.2 L/yr - ₹4.3 L/yr

arrow icon 69% less
Logo
unlock blur

₹4 L/yr - ₹10.9 L/yr

arrow icon 50% less
1 job opening
unlock blur

₹13 L/yr - ₹20 L/yr

arrow icon 26% more
unlock blur

₹1.5 L/yr - ₹5 L/yr

arrow icon 75% less
unlock blur

₹3 L/yr - ₹6 L/yr

arrow icon 64% less
Asic Design Verification Engineer salary at Yoctozant Technologies ranges between ₹10.8 Lakhs to ₹13.8 Lakhs per year for employees with 3 years of experience. Salary estimates are based on 1 latest salaries received from various employees of Yoctozant Technologies.

Similar Designation salaries in Yoctozant Technologies

unlock blur
₹7 L/yr - ₹10 L/yr
unlock blur
₹5 L/yr - ₹9.5 L/yr
Asic Verification Engineer Salary
(AmbitionBox Estimate)
unlock blur
₹9.9 L/yr - ₹12.6 L/yr
Verification Engineer Salary
(AmbitionBox Estimate)
unlock blur
₹4.7 L/yr - ₹6 L/yr
Analog Layout Engineer Salary
(AmbitionBox Estimate)
unlock blur
₹4.5 L/yr - ₹5.8 L/yr

Tell us how to improve this page.

Yoctozant Technologies Asic Design Verification Engineer salary in India ranges between ₹10.8 Lakhs to ₹13.8 Lakhs. This is an estimate based on latest salaries received from employees of Yoctozant Technologies.