Physical Design Engineer (3-11 yrs)

We are seeking a skilled and motivated Physical Design Engineer to join our team and contribute to the design and implementation of cutting-edge semiconductor chips. The ideal candidate will have expertise in digital physical design flows, with hands-on experience using Cadence Innovus tools for floorplanning, placement, routing, and timing closure.

Key Responsibilities :

- Perform end-to-end physical design tasks, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and optimization.

- Timing Closure : Conduct static timing analysis (STA) and resolve issues related to setup, hold, noise, and crosstalk.

- Work on power grid design, IR drop analysis, and low-power techniques such as clock gating, power gating, and multi-Vt design.

- Utilize Cadence Innovus for physical implementation, optimization, and achieving design closure.

- Design Verification : Collaborate with verification teams to ensure physical design meets DRC, LVS, and electromigration (EM/IR) requirements.

- EDA Tool Integration : Optimize Innovus scripts for efficient flow execution and improve overall runtime and quality.

- Work closely with RTL designers, DFT engineers, and package teams to address constraints, floorplan adjustments, and timing challenges.

- Develop physical design strategies for advanced nodes (e.g., 7nm, 5nm, or below) while addressing challenges such as congestion, variability, and manufacturability.

Qualifications :

Educational Background : Bachelor's or Master's degree in Computer Engineering, or a related field.

Experience :

- 3+ years of experience in digital physical design.

- Proven experience with Cadence Innovus and familiarity with other