ASIC Digital Design, Staff Engineer

• The candidate will be part of the R&D in Solutions Group, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP verification using the latest verification methodology flows.

Job Description

• The candidate will be part of the DesignWare IP Verification R&D team at Synopsys.
• He/She will be expected to specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores.
• He/ She will work closely with RTL designers and be part of a global team of expert Verification Engineers.

Will be working on the next generation connectivity protocols for Commercial, Enterprise and Automotive applications

Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding, debugging, FC coding and analysis, meeting quality metric goals and regression management.

Requirements :

- Must have BSEE in EE with 4 to 8+ years of relevant experience or MSEE with 3 to 7+ years of relevant experience in the following areas:
- Must have experience in developing HVL (System Verilog) based test environments, developing, and implementing test plans, implementing, and extracting verification metrics such as functional coverage.
- Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools.
- Exposure to verification methodologies such as VMM/OVM/UVM/ is required.
- Exposure to Formal verification methodologies is highly desirable.
- Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI), SD/eMMC, Ethernet, DDR, PCIe, USB
- Familiarity with HDLs such as Verilog and scripting languages such as Perl, TCL, Python is highly desired.
- Exposure to IP design and verification processes including VIP development is an added advantage.
- There will be strong focus on functional coverage-driven methodology. So, the corresponding mindset is a must.
- It is essential that the individual has good written and oral communication skills and can demonstrate good analysis, debug and problem-solving skills and show high levels of initiative.