Test & Validation Engineering, Sr Engineer

This position offers a wonderful opportunity to work on most challenging technical problems in verification domain and innovative technologies under Synopsys Verification Platform. Looking for an experienced and motivated professional who enjoys problem solving, open to continuous learning, passionate to work on cutting edge technologies and has excellent communication skills. It gives exposure to the breadth of HDL/HVL, methodologies, static and formal verification, dynamic simulation aspects including debug and experience in working in a diverse environment where interaction with domain experts across global locations will be involved.

Key Requirements

• Experience: bachelors degree in Electronics with 3+ Years or masters degree in Electronics with 2+ Years
• Experience in verification technologies ( Lint, Clock/Reset Domain Crossing, Simulation, UVM, SVA, LRM understanding )
• Exposure to Synopsys EDA tools (SpyGlass, VC SpyGlass, VCS, Verdi) would be added advantage
• Solid fundamentals in Digital design, HDLs (Verilog/VHDL) and System Verilog
• Excellent written and oral communication skills is a must as the role requires interfacing global teams, proposing solutions
• Must have working knowledge on UNIX, Tcl and/or any other scripting language to be effective
• Team player, partners with multiple stakeholders, has attention to detail and innovative mindset
• Motivated, doer and self-organized team worker with good social communication skills
• Open to travel, ability to multi-task, be detail-oriented