R&D Engineering, Staff Engineer

What You'll Be Doing:

• Designing and developing emulation models.
• Implementing and verifying digital designs using System Verilog and Verilog.
• Developing scripts in Perl, TCL, or other languages.
• Collaborating with cross-functional teams.
• Conducting protocol verification for various standards.
• Utilizing UVM for design validation.

• Enhancing emulation model efficiency.
• Contributing to high-performance silicon chips.
• Improving design reliability through verification.
• Streamlining workflows with automation.
• Ensuring protocol compliance.
• Driving technological advancements.

• B.E / M.E. in Electronic & Communication / Computer Science Engineering.
• Proficiency in C/C++ and OOPS.
• Knowledge of digital design and HDL languages.
• Experience with scripting languages.
• Familiarity with multiple protocols and UVM.

• Effective communicator.
• Team player.
• Resourceful and detail-oriented.
• Innovative problem-solver.
• Adaptable learner.

Rewards and Benefits: