Sykatiya Technologies - Lead Design Verification Engineer/Manager/Director - ASIC/VLSI (15-20 yrs)

Roles & Responsibilities :

1. You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.

2. Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology.

3. Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity.

4. Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation.

5. Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology

Required Skills :

1. Desired experience: 4 years in real time projects

2. ASIC Verification using System Verilog

3. Experience in constrained-random verification is a strong plus

4. Experience with verification methodology like OVM/VMM/UVM

5. Perl/Tcl scripting is strongly preferred

6. Strong problem solving and ASIC debugging skills

Education Background :

B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Instrumentation Engineering.