DFT Lead/Manager (12-20 yrs)

Job Description :

- Hands on experience with DFT 8-15 Years

- Should have experience in DFT and ATPG activities on SoC designs with expertise in MBIST Planning /Insertion, Partitioning Design for Scan, Scan Insertion, Compression, Wrapper Insertion, ATPG Simulations.

- Expertise in handling Flat/Hierarchical SoC designs

- Expertise in JTAG, Boundary Scan, STA Constraints creation for DFT modes.

- Develop Test Programs and debug SoC controllers for HDD and/or SSD

- Perform data collection, analysis and characterization report generation of all products

- Design of reliability hardware working in close coordination with TE

- Deploying products in to HVM (High Volume Manufacturing) at OSAT locations

- Work with offshore product engineers for release and manage of ATE (Automated Test Experiments) test programs at production test facilities

- Conduct high volume test data analysis using data analysis tools

- Work closely with test development engineers to improve production yield, test related issues and cycle times improvements

- Defining and executing DFT-related tool flows, spanning insertion, ATPG, as well as DFT requirements in front-to- back SoC implementation flows

- Test vector planning for bring-up and production, and hand-on ATE bring-up experience

- Achieving high coverage via SAF, TDF, as well as knowledge of other techniques such as Small Delay Defects, Path testing, LOC/LOS, etc.

- Tessent, DFTC, TCL/PERL, IEEE 1149 and 1687, Primetime, SpyGlass, Verilog simulation including SDF, and Advantest ATE

- Architecting automation strategies that align with third party DFT tools and creating further efficiencies

- Leading large DFT/ATPG teams

- Defining/bring-up of DFT architecture including hierarchical core/chip based flows and pattern retargeting

- Experience with large device test on ATE and with architecting DFT strategies in support of multi-core and parallel testing

Qualifications : B.E/B. Tech/M.E/M. Tech