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Senior Engineer I - DFT
Open-Silicon
posted 4d ago
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Job Description
The Opportunity
Were looking for the Wavemakers of tomorrow.
What youll do :
- Be a senior member of Alphawave central DFT methodology group responsible for developing flows across all company departments and projects
- Architect methodologies and flows for an integrated, RTL-centric "shift left" DFT environment across company IPs, chiplets and SoC designs.
- Develop automated verification test bench and sequence creation for DFT IP. Architecting end-2-end verification solutions from static design checks, through formal and sequence-based verification.
- Build IP/block and SoC level scan insertion flows and script ATPG retargeting procedures. Creating automated QoR checks for implementation quality control.
- Write static timing constraints, create waivers, and devise flows for bullet proof timing checks
- Hiring, training and leading DFT engineers in daily tasks and activities to fulfill company road map.
What youll need:
- Engineer with proven technical and people management skills
- Collaborative team player, and out of the box mindset
- Good understanding in Verilog/VHDL and System Verilog
- Exposure with CAD and automation. Good exposure for using Perl techniques in creating generic codes. Knowledge of TCL and Python.
- Extensively experienced with main DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687) and BIST techniques (memory BIST, logic BIST, interconnect BISTs)
- Track record in integrating custom made DFT logic for complex SoCs (System-On-Chip) and CoWoS (Chip-On-Wafer-On-Substrate) designs.
- Experience in SoC and IP/Block level scan insertion and ATPG, simulation of zero delay and SDF annotated test sequences.
- Experience in scripting/reviewing SCAN/MBIST timing constraints.
- Developing DFT rule bases and DFT-DRC checks with spyglass are valuable additions.
Good to have:
- Bachelors degree in engineering science, Electrical and Computer Engineering or Computer Science
- 4+ years of experience in complex SoC designs in RTL, DFT or FE capacity. Candidates with less experience may be considered for other senior technical roles.
- Experience to various DFT EDA tools from Tessent, SNPS and Cadence
- Experience in core wrapping, pattern retargeting & packetizing ATPG techniques. SSN knowledge.
Diversity & Inclusivity
Alphawave Semi is based in one of the most diverse countries in the world. This includes differences related to race, ethnicity, national origin, gender, gender expression and presentation, sexual orientation, religion, age, ability and socioeconomic status. To us, diversity is one of our strongest assets to our organization. We commit ourselves to promoting the recognition and appreciation of our diverse and rich culture. We believe it is critical to our success to promote freedom of thought and opinion in a respectful environment. Our decisions are rooted in respectfully considering each other s thoughts and opinions and working towards a greater common goal.
Accommodation
Alphawave Semi is an equal opportunity employer and welcomes applications from all qualified individuals, including visible minorities, Indigenous People, and persons with disabilities. We welcome and encourage applications from people with disabilities. If, as a qualified job applicant, you request an accommodation, Alphawave Semi will consult with you to provide reasonable accommodations according to your specific needs. If you wish to make a request, you will be provided an opportunity if you re application is selected to proceed in our hiring process.
Employment Type: Full Time, Permanent
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What people at Open-Silicon are saying
Senior Engineer salary at Open-Silicon
reported by
2
employees
₹22.9
L/yr - ₹29.3
L/yr
188%
more
than the average Senior Engineer Salary in India
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What Open-Silicon employees are saying about work life
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Open-Silicon Benefits
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