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Premium Employer

Advanced Micro Devices

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3.7

based on 257 Reviews

Video summary

226 Advanced Micro Devices Jobs

DFT Engineer

Advanced Micro Devices, Inc

3.7

based on 257 Reviews

2-7 years

Bangalore / Bengaluru

1 vacancy

DFT Engineer

Advanced Micro Devices

posted 4mon ago

Job Role Insights

Flexible timing

Key skills for the job

Social Work Recruitment Linux Administration Analytical Chemistry Perl Digital Design

+ 3 more

Job Description

As a member of the RTG SoC DFT Team ( part of DCG BU) , the successful candidate will own the DFT responsibilities for the next gen of AMD SoCs.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

The candidate must have thorough knowledge of DFT basics such as scan insertion, fault models, ATPG, BIST techniques, and on-chip compression techniques that reduce test time and tester memory. Need to work with product engineering team for Silicon Bring-up and also support post-silicon debug.

Interfacing with the design teams to ensure DFT design rules and guidelines are met
Interact with PD and Front End Integration team for Scan Insertion
Generating high quality manufacturing test patterns for stuck-at, transition fault models and CA model
Simulating and verifying the ATPG and LBIST patterns
Working with the product engineering teams on the delivery of manufacturing test patterns
Developing, enhancing and maintaining scripts as necessary
Able to technically guide and mentor junior folks in the team

PREFERRED EXPERIENCE:

Experience in creating and implementing complex chip-level DFT architecture
Experience in DFT implementation including Scan insertion, ATPG and Simulations
Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression
Experience in debugging low coverage and DRC fixes
Proficient in logic design using Verilog
Experience of debugging test pattern issues
Support the Silicon bringup activities to guarantee highest stability of the test pattern
SSN Knowledge is a plus
Knowledge of MBIST is a plus
Knowledge of synthesis is a plus
Experience with post-silicon debug
Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc
Any Tessent Scan/ATPG certifications is a plus
Excellent presentation and inter-communication skills.