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Staff Engineer I - STA and Synthesis
Open-Silicon
posted 26d ago
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Key skills for the job
Job Description
The Opportunity
Were looking for the Wavemakers of tomorrow.
- Lead the execution of static timing analysis and synthesis tasks for complex ASIC designs, ensuring adherence to project schedules and performance targets.
- Collaborate closely with design teams to understand timing requirements, address timing constraints, and optimize design performance across digital and analog boundaries.
- Proficient with the use of FM/LEC to resolve equivalence issues, and also implement ECOs.
- Develop and maintain comprehensive timing constraint sets, leveraging expertise in industry-standard scripting languages such as Python or Perl to automate constraint generation and validation processes.
- Interface with cross-functional teams including physical design, verification, and system integration to resolve timing-related issues and drive design closure.
- Apply deep understanding of flow methodologies and best practices to streamline design implementation processes and improve overall design efficiency.
- Demonstrate strong communication skills to effectively articulate timing analysis results, provide timely updates on project status, and collaborate with stakeholders to resolve technical challenges.
- Stay abreast of emerging technologies and industry trends, continuously enhancing skills and knowledge to remain at the forefront of ASIC design methodologies and practices.
- Advanced RTL Design Skills
- Proficiency in Register Transfer Level (RTL) design
- Optimization for area, power, and performance
- Deep Understanding of Clock Domain Crossing (CDC)
- Techniques for reliable data transfer between clock domains
- Synchronizer design and analysis
- Deep Understanding of RTL LINT Errors/Warnings
- Expertise in Low Power Design Techniques
- Power optimization methodologies such as clock gating, power gating, etc.
- Analysis and optimization for low power operation
- Proficiency in EDA Tools
- Experience with synthesis, static timing analysis, and physical design tools
- Knowledge of Synopsys Design Compiler, Cadence Encounter, Fusion Compiler etc.
- Knowledge of ASIC Design Flow
- Understanding of the end-to-end ASIC design flow
- Familiarity with Design for Testability (DFT) techniques
- Problem-Solving and Debugging Skills
- Analysis of complex timing and synthesis issues
- Debugging RTL and gate-level simulations
- Team Collaboration and Leadership
- Effective collaboration in cross-functional teams
- Leadership skills for project management and mentorship
- Continuous Learning and Adaptability
- Stay updated with advancements in ASIC design methodologies
- Adaptability to evolving project requirements and industry trends
Diversity Inclusivity
Alphawave Semi is based in one of the most diverse countries in the world. This includes differences related to race, ethnicity, national origin, gender, gender expression and presentation, sexual orientation, religion, age, ability and socioeconomic status. To us, diversity is one of our strongest assets to our organization. We commit ourselves to promoting the recognition and appreciation of our diverse and rich culture. We believe it is critical to our success to promote freedom of thought and opinion in a respectful environment. Our decisions are rooted in respectfully considering each other s thoughts and opinions and working towards a greater common goal.
Accommodation
Alphawave Semi is an equal opportunity employer and welcomes applications from all qualified individuals, including visible minorities, Indigenous People, and persons with disabilities. We welcome and encourage applications from people with disabilities. If, as a qualified job applicant, you request an accommodation, Alphawave Semi will consult with you to provide reasonable accommodations according to your specific needs. If you wish to make a request, you will be provided an opportunity if you re application is selected to proceed in our hiring process.
Employment Type: Full Time, Permanent
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