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81 Hanker Systems Jobs
Verification Engineer
Hanker Systems
posted 26d ago
Job Description
Well versed in (Digital design, SV, UVM).
Experience in DDR, PHY protocols.
Responsibilities:
Develop and execute comprehensive verification plans and testbenches using UVM methodologies.
Write and debug complex SystemVerilog test code for functional, performance, and regression testing.
Collaborate with design engineers to understand and analyze design specifications.
Identify, debug, and isolate design issues.
Participate in design reviews and contribute to design improvements.
Maintain and enhance existing verification environments.
Stay abreast of the latest verification methodologies and tools.
Experience in DDR, PHY protocols.
Responsibilities:
Develop and execute comprehensive verification plans and testbenches using UVM methodologies.
Write and debug complex SystemVerilog test code for functional, performance, and regression testing.
Collaborate with design engineers to understand and analyze design specifications.
Identify, debug, and isolate design issues.
Participate in design reviews and contribute to design improvements.
Maintain and enhance existing verification environments.
Stay abreast of the latest verification methodologies and tools.
Employment Type: Full Time, Permanent
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