Eximietas Design - Senior Design Verification Engineer (5-15 yrs)

Job Description :

- Hands-on experience in SOC Design Verification.

- Expertise in UVM (Universal Verification Methodology) and System Verilog.

- Prior experience working on IP level and SOC level verification projects.

- Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).

- Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.

- Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.

- Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.

- Proficiency in scripting languages such as shell, Makefile, and Perl.

- Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment