Hiring Design Verification, RTL Design Opportunities India & USA

Design Verification & RTL Design Opportunities India & USA 🌎

📍 Locations:
🇮🇳 India – Bangalore / Hyderabad / Noida
🇺🇸 USA – Onsite (Any valid work permit required)

🛠 Experience: 3 to 20 years
📄 Employment Type: Full-time

🇺🇸 Open Positions – USA (Onsite, Work Permit Required)

🔹 Ethernet Design Verification – 5+ years of experience
🔹 PCIe Design Verification – 5+ years of experience
🔹 Generic Design Verification – 6+ years of experience
🔹 RTL Design – 6+ years of experience (Shorter Notice Period Preferred)

🇮🇳 Open Positions – India (Bangalore / Hyderabad / Noida)

ExpSkills

5-13 yrsPCIe (Root Complex, SR-IOV), DDR, CHI-based Coherent NoC10-14 yrsLow-power design, UPF5-8 yrsPCIe / UCIe5-8 yrsARM Cortex-M / RISC / C3-10 yrsAMS15-20 yrsProgram Management3-6 yrsGLS / C3+ yrsCHI / ACE / NoC / FuSa5+ yrsPCIe / CXL / UCIe3+ yrsDDR / LPDDR / HBM3+ yrsNIC / PCIe / CXL / DDR4+ yrsUVM / AXI5+ yrsSoC (C-based), Ethernet, GLS, SerDes, Python8+ yrsPCIe10+ yrsLeadership roles in Design Verification / RTL

🔍 Key Skills Required

✅ Design Verification: SystemVerilog, UVM, Verilog, Testbench development, ASIC/FPGA verification
✅ RTL Design: Verilog, VHDL, Logic Design, Microarchitecture, SoC/ASIC Design
✅ Protocols: PCIe, Ethernet, DDR, LPDDR, UFS, HSIO, AMS, CXL, CHI, NoC, AXI
✅ Tools: Synopsys, Cadence, Mentor Graphics EDA tools

🚀 Why Join Us?

✅ Work on cutting-edge semiconductor projects with leading global clients
✅ Competitive salary & benefits
✅ Growth opportunities in top-tier VLSI teams

📩 Interested? Send your resume to: pkalavathi@mirafra.comRole & responsibilities