Design Verification Engineer - System Verilog/UVM (9-12 yrs)

Job Title : VLSI Front-End Design Verification Engineer

Experience : 9+ Years

Location : Bangalore / Hyderabad

Role Summary :

We are looking for a seasoned VLSI Front-End Design Verification Engineer with expertise in SystemVerilog (SV) and UVM-based verification methodologies. The ideal candidate will have a strong technical background, proven experience in leading teams, and hands-on verification expertise. Experience with protocols is a plus.

Key Responsibilities :

1. Design Verification (DV) :

- Execute front-end design verification using SystemVerilog (SV) and UVM frameworks.

- Develop, implement, and debug verification environments and test plans.

2. Protocol Expertise : Experience in working with any industry-standard protocol will be an added advantage.

3. Leadership and Team Handling :

- Manage and mentor a team of verification engineers, ensuring deliverables are met with high quality and within timelines.

- Act as a technical lead, guiding and supporting team members in resolving technical challenges.

4. Collaboration : Work closely with design and architecture teams to ensure verification coverage and identify design bottlenecks.

5. Process Improvements : Drive innovations in verification processes and methodologies for improved efficiency and quality.

Technical Skills Required :

- Proficiency in SystemVerilog (SV) and UVM-based verification methodologies.

- Hands-on experience with verification environments, test benches, and debugging tools.

- Knowledge of protocols like PCIe, USB, Ethernet, AMBA, etc., is a plus.

- Strong analytical and problem-solving skills.

Key Attributes :

- Solid technical background with a passion for VLSI design verification.

- Proven ability to handle complex projects and lead teams effectively.

- Excellent communication and interpersonal skills.