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Sr Principal RTL Design Engineer
12-20 years
Bangalore / Bengaluru
1 vacancy
Sr Principal RTL Design Engineer
Cadence Design Systems
posted 5mon ago
Job Role Insights
Flexible timing
Key skills for the job
Job Description
- 12+ years of experience in ASIC design
- Proficient in Verilog coding, RTL design and complex control path and data path designs
- Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA
- Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints
- Experience in writing Verilog testbench and running simulations.
Employment Type: Full Time, Permanent
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