Cadence Design Systems - Physical Design Engineer - ASIC/SoC Design (3-5 yrs)

Role Overview :

We are looking for a highly technical and innovative Physical Design Engineer to join our team.

In this role, you will be at the forefront of advanced process node technologies (7nm, 5nm, 3nm, 2nm), driving the development and optimization of EDA flows and physical implementation strategies for high-performance, power-efficient IP cores.

Key Responsibilities :

EDA Flow Development & Automation :

- Architect, develop, and maintain advanced EDA flows and scripts for end-to-end physical design implementation.

- Drive automation in design flows to streamline processes and enhance efficiency.

PPA Optimization :

- Characterize and optimize PPA (Performance, Power, Area) for cutting-edge IP cores in advanced technology nodes.

- Innovate methodologies to push the envelope of performance and power efficiency.

Digital Design Implementation :

- Implement and validate physical design using Cadence EDA tools such as Genus, Innovus, Tempus, and Voltus.

- Execute detailed floorplanning, placement, routing, timing closure, and power analysis.

Regression Infrastructure Management :

- Build and manage robust regression systems to monitor RTL/flow quality and PPA metrics across multiple designs.

Customer Engagement :

- Perform benchmarking of PPAs and contribute to customer engagements by delivering optimized, best-in-class IP solutions.

Technical Skills & Qualifications :

Education :

- MS/MTech/BE/BTech in Electronics, Computer Science, or related fields from reputed institutes.

Experience :

- 3+ years of hands-on experience in an ASIC/SoC design environment, specializing in physical design.

Core Expertise :

- Strong command of the ASIC design flow : synthesis, physical implementation, timing analysis, and formal verification.

- Expertise in advanced process nodes (7nm and below).

- Proficiency in using Cadence tools (Genus, Innovus, Tempus, Voltus) and other backend EDA tools.

Programming & Scripting :

- Advanced skills in Python, TCL, Perl, and Unix shell scripting for automation and debugging.

Domain Knowledge :

- Deep understanding of digital logic design, processor architecture, and computer systems.

- Proven track record in PPA benchmarking and optimization.

Preferred Skills :

- Familiarity with machine learning techniques for design flow optimization.

- Experience with multi-clock domain designs and low-power methodologies.

- Knowledge of parallel processing and distributed computing for EDA tool acceleration.

What We Offer :

- Opportunity to work on bleeding-edge technology nodes and contribute to innovative solutions.

- A collaborative environment with a focus on continuous learning and technical excellence.