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Tessolve Semiconductor Hardware Engineer Interview Questions and Answers

Updated 4 Feb 2024

Tessolve Semiconductor Hardware Engineer Interview Experiences

1 interview found

Interview experience
5
Excellent
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
-

I applied via Referral and was interviewed before Feb 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

Questions on basic electronics

Round 2 - Technical 

(1 Question)

  • Q1. About digital electronics power electronics

Interview questions from similar companies

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
No response

I applied via LinkedIn and was interviewed in Jul 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. What kind FPGAs used, tell me difference
  • Ans. 

    FPGAs are Field-Programmable Gate Arrays used in hardware design. They can be categorized as SRAM-based, Flash-based, or Antifuse-based.

    • SRAM-based FPGAs are volatile and require reprogramming every time they power up. Examples include Xilinx Virtex series.

    • Flash-based FPGAs are non-volatile and retain their configuration even when powered off. Examples include Actel ProASIC3 series.

    • Antifuse-based FPGAs are OTP (One-Time...

  • Answered by AI
  • Q2. Calculation of Decoupling analysis
  • Ans. 

    Decoupling analysis involves calculating the required capacitance to maintain stable voltage levels in a circuit.

    • Decoupling analysis is essential for ensuring stable power supply in electronic circuits.

    • It involves calculating the amount of capacitance needed to filter out noise and maintain voltage levels.

    • Decoupling capacitors are placed strategically in a circuit to provide this filtering effect.

    • The formula for calcul...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare based on company where you are applying

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Jun 2024. There were 2 interview rounds.

Round 1 - Aptitude Test 

Basic ece ques and apti

Round 2 - Technical 

(2 Questions)

  • Q1. What are flip flops and latches
  • Ans. 

    Flip flops and latches are sequential logic circuits used in digital electronics to store and transfer data.

    • Flip flops are clocked circuits that store one bit of data, while latches are level-sensitive circuits that store data as long as the enable signal is active.

    • Flip flops are edge-triggered, meaning they change state on a clock edge, while latches are level-triggered, changing state as long as the enable signal is ...

  • Answered by AI
  • Q2. Verilog projects

Interview Preparation Tips

Interview preparation tips for other job seekers - prepare well gate sub digital and verilog
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Aptitude Test 

Aptitude, Digital Electronics.

Interview experience
5
Excellent
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Aptitude Test 

Questions on dgital electronics and circuits

Round 3 - Technical 

(1 Question)

  • Q1. Questions on digital electronics , STA and FSM and Verilog
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
No response

I applied via LinkedIn and was interviewed in Jul 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. What kind FPGAs used, tell me difference
  • Ans. 

    FPGAs are Field-Programmable Gate Arrays used in hardware design. They can be categorized as SRAM-based, Flash-based, or Antifuse-based.

    • SRAM-based FPGAs are volatile and require reprogramming every time they power up. Examples include Xilinx Virtex series.

    • Flash-based FPGAs are non-volatile and retain their configuration even when powered off. Examples include Actel ProASIC3 series.

    • Antifuse-based FPGAs are OTP (One-Time...

  • Answered by AI
  • Q2. Calculation of Decoupling analysis
  • Ans. 

    Decoupling analysis involves calculating the required capacitance to maintain stable voltage levels in a circuit.

    • Decoupling analysis is essential for ensuring stable power supply in electronic circuits.

    • It involves calculating the amount of capacitance needed to filter out noise and maintain voltage levels.

    • Decoupling capacitors are placed strategically in a circuit to provide this filtering effect.

    • The formula for calcul...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare based on company where you are applying

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via Campus Placement and was interviewed before Apr 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

Digital Electronics, CMOS, Aptitude, C programming

Round 2 - Technical 

(1 Question)

  • Q1. Verilog, VLSI Design Flow, CMOS basics
Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Aptitude Test 

Aptitude, Digital Electronics.

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Selected Selected

I applied via campus placement at Vellore Institute of Technology (VIT) and was interviewed in Jan 2023. There were 3 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Don’t add your photo or details such as gender, age, and address in your resume. These details do not add any value.
View all tips
Round 2 - Aptitude Test 

Given all king of aptitude part

Round 3 - Technical 

(2 Questions)

  • Q1. Analog and digital electronics
  • Q2. Draw the bode plot for CS amplifier
  • Ans. 

    Bode plot for CS amplifier shows gain and phase response with frequency.

    • Bode plot consists of two plots - one for gain (in dB) and one for phase shift (in degrees) vs frequency.

    • The gain plot typically shows a high-pass filter response with a peak at the resonant frequency.

    • The phase plot shows a 180 degree phase shift at the resonant frequency.

    • Bode plots are useful for analyzing frequency response of amplifiers and filt

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Stick on basics.
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Jun 2024. There were 2 interview rounds.

Round 1 - Aptitude Test 

Basic ece ques and apti

Round 2 - Technical 

(2 Questions)

  • Q1. What are flip flops and latches
  • Ans. 

    Flip flops and latches are sequential logic circuits used in digital electronics to store and transfer data.

    • Flip flops are clocked circuits that store one bit of data, while latches are level-sensitive circuits that store data as long as the enable signal is active.

    • Flip flops are edge-triggered, meaning they change state on a clock edge, while latches are level-triggered, changing state as long as the enable signal is ...

  • Answered by AI
  • Q2. Verilog projects

Interview Preparation Tips

Interview preparation tips for other job seekers - prepare well gate sub digital and verilog

Tessolve Semiconductor Interview FAQs

How many rounds are there in Tessolve Semiconductor Hardware Engineer interview?
Tessolve Semiconductor interview process usually has 2 rounds. The most common rounds in the Tessolve Semiconductor interview process are Aptitude Test and Technical.

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3.5

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