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Samsung Semiconductor Senior Hardware Engineer Interview Questions and Answers

Updated 2 Jun 2022

Samsung Semiconductor Senior Hardware Engineer Interview Experiences

1 interview found

I applied via campus placement at Indian Institute of Technology (IIT), Kharagpur and was interviewed before Jun 2021. There was 1 interview round.

Round 1 - Technical 

(1 Question)

  • Q1. PPO interview for SSIR (hardware) 2021: Background: IIT (old), dual degree, ECE 1. Puzzles from GFG (top 50) 2. Mod n counter, up/down counter design 3. Frequency divider: f/2, f/1.5, f/3, f/2.5, f/5, f/7...

Interview Preparation Tips

Interview preparation tips for other job seekers - Basics should be strong. STA, verilog, digital design, cv projects, little vlsi

Interview questions from similar companies

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. What is the difference between latch and flip flop
  • Ans. 

    Latch is level triggered and stores data temporarily, while flip flop is edge triggered and stores data permanently.

    • Latch is level triggered, while flip flop is edge triggered

    • Latch stores data temporarily, while flip flop stores data permanently

    • Latch requires continuous input to hold the output, while flip flop retains the output until a new input is received

  • Answered by AI
  • Q2. Draw or gate using nand gates
  • Ans. 

    A NAND gate can be used to create a NOR gate by connecting two NAND gates in series.

    • Connect the outputs of two NAND gates together

    • Connect the inputs of the two NAND gates to the same input signal

    • The output of the combined NAND gates will act as a NOR gate

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Basic question on digital and some analog concepts
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via campus placement at PSG College of Technology, Coimbatore and was interviewed in Jul 2024. There were 3 interview rounds.

Round 1 - Aptitude Test 

It consisted of aptitude questions, then OS C 1mrks, which were re GATE questions. No coding, I chose hardware role, so questions were from digital electronics too. prepare the gate questions for these subjects

Round 2 - Technical 

(2 Questions)

  • Q1. Question were from vlsi and SOC design
  • Q2. Then questions on optimizations in vlsi were asked.
Round 3 - HR 

(2 Questions)

  • Q1. Family and background check
  • Q2. Resume and projects

Interview Preparation Tips

Interview preparation tips for other job seekers - prepare gate questions. negative marking in round 1, so choose wisely. be thorough in any one domain so you can answer all the questions
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
2-4 weeks
Result
No response

I applied via LinkedIn and was interviewed in Jul 2024. There was 1 interview round.

Round 1 - Technical 

(2 Questions)

  • Q1. What kind FPGAs used, tell me difference
  • Ans. 

    FPGAs are Field-Programmable Gate Arrays used in hardware design. They can be categorized as SRAM-based, Flash-based, or Antifuse-based.

    • SRAM-based FPGAs are volatile and require reprogramming every time they power up. Examples include Xilinx Virtex series.

    • Flash-based FPGAs are non-volatile and retain their configuration even when powered off. Examples include Actel ProASIC3 series.

    • Antifuse-based FPGAs are OTP (One-Time...

  • Answered by AI
  • Q2. Calculation of Decoupling analysis
  • Ans. 

    Decoupling analysis involves calculating the required capacitance to maintain stable voltage levels in a circuit.

    • Decoupling analysis is essential for ensuring stable power supply in electronic circuits.

    • It involves calculating the amount of capacitance needed to filter out noise and maintain voltage levels.

    • Decoupling capacitors are placed strategically in a circuit to provide this filtering effect.

    • The formula for calcul...

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Prepare based on company where you are applying

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Aptitude Test 

Aptitude, Digital Electronics.

I applied via Campus Placement and was interviewed in Jul 2022. There were 2 interview rounds.

Round 1 - Aptitude Test 

Digital Electronics, verilog basics,C language basics,

Round 2 - Technical 

(2 Questions)

  • Q1. Project description, digital system design for start bit detector in UART
  • Ans. 

    Designing a digital system for detecting start bit in UART communication

    • The start bit is the first bit in a UART transmission and is always a logic low

    • The system should sample the incoming data at a rate higher than the baud rate to accurately detect the start bit

    • A shift register can be used to store the incoming data and detect the start bit

    • The system should also check for framing errors and parity errors

  • Answered by AI
  • Q2. Project description, latch based circuit and flip flop based circuits, 1 puzzle

Interview Preparation Tips

Interview preparation tips for other job seekers - Very deep understanding of digital electronics is a must

Skills evaluated in this interview

Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via Campus Placement and was interviewed in Apr 2024. There were 3 interview rounds.

Round 1 - Aptitude Test 

Basic apptitude and digital and analog mcqs

Round 2 - Technical 

(1 Question)

  • Q1. Design a 3 input xor gate using 4:1mux
  • Ans. 

    Use a 4:1 mux to create a 3 input XOR gate.

    • Connect two of the inputs to the select lines of the mux.

    • Connect the third input to one of the data inputs of the mux.

    • Connect the other data input of the mux to the output of an XOR gate between the first two inputs.

    • Use the output of the mux as the output of the 3 input XOR gate.

  • Answered by AI
Round 3 - HR 

(1 Question)

  • Q1. Wasn't selected to hr round
Interview experience
1
Bad
Difficulty level
-
Process Duration
-
Result
-
Round 1 - Technical 

(2 Questions)

  • Q1. Cache coherency
  • Q2. MIPS
Interview experience
4
Good
Difficulty level
Moderate
Process Duration
Less than 2 weeks
Result
Not Selected

I applied via campus placement at Indraprastha Institute of Information Technology (IIIT), Delhi and was interviewed in Jul 2023. There were 2 interview rounds.

Round 1 - Aptitude Test 

Logical, Quant and English questions. C based theory questions, and digital electronics.

Round 2 - Technical 

(3 Questions)

  • Q1. Project related questions, SRAM, DRAM device based questions.
  • Q2. CMOS based questions to determine the drain voltage of a transistor.
  • Q3. Question about read cycle timing graphs in AHB.

Interview Preparation Tips

Interview preparation tips for other job seekers - Be well aware about all what you have stated in your resume.

I applied via campus placement at Pachaiyappas College, Chennai and was interviewed before Oct 2021. There were 3 interview rounds.

Round 1 - Resume Shortlist 
Pro Tip by AmbitionBox:
Keep your resume crisp and to the point. A recruiter looks at your resume for an average of 6 seconds, make sure to leave the best impression.
View all tips
Round 2 - Aptitude Test 

Based on Electronics, Aptitude and Software

Round 3 - Technical 

(3 Questions)

  • Q1. Explain the working of D flip flop
  • Ans. 

    D flip flop is a digital circuit that stores a single bit of data and is used in sequential logic circuits.

    • D flip flop has a data input (D), a clock input (CLK), a set input (S), and a reset input (R).

    • When the clock input is high, the value of D is transferred to the output Q.

    • When the set input is high, the output Q is set to high.

    • When the reset input is high, the output Q is reset to low.

    • D flip flop is used in applica...

  • Answered by AI
  • Q2. Finding factorial using C
  • Ans. 

    Factorial can be found using a loop or recursion in C programming language.

    • Use a loop to multiply the numbers from 1 to n to find the factorial of n.

    • Use recursion to call the function itself with n-1 until n=1.

    • Handle edge cases such as negative numbers and 0.

    • Example: int factorial(int n) { if(n<=1) return 1; return n*factorial(n-1); }

    • Example: int factorial(int n) { int fact=1; for(int i=1;i<=n;i++) fact*=i; return fact

  • Answered by AI
  • Q3. Find duplicates in a string
  • Ans. 

    To find duplicates in a string, we can use a hash table to keep track of the frequency of each character.

    • Iterate through the string and add each character to the hash table with its frequency

    • If a character already exists in the hash table, it is a duplicate

    • Return a list of all the duplicate characters found

  • Answered by AI

Interview Preparation Tips

Interview preparation tips for other job seekers - Go through basic electronics(ECE) if you are interested in hardware else practice coding

Skills evaluated in this interview

Samsung Semiconductor Interview FAQs

How many rounds are there in Samsung Semiconductor Senior Hardware Engineer interview?
Samsung Semiconductor interview process usually has 1 rounds. The most common rounds in the Samsung Semiconductor interview process are Technical.

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Samsung Semiconductor Senior Hardware Engineer Salary
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₹15 L/yr - ₹25 L/yr
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