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I applied via Recruitment Consulltant and was interviewed before Nov 2023. There was 1 interview round.
I am a VLSI Design Engineer with a strong background in digital and analog circuit design.
Graduated with a degree in Electrical Engineering
Proficient in Verilog and VHDL for RTL design
Experience with ASIC and FPGA design
Skilled in using EDA tools like Cadence and Synopsys
Worked on projects involving low power design techniques
Moore machines have outputs dependent only on present state, while Mealy machines have outputs dependent on present state and inputs.
Moore machines have outputs that depend only on the present state of the machine.
Mealy machines have outputs that depend on both the present state and the inputs to the machine.
Moore machines are simpler to design and analyze compared to Mealy machines.
Mealy machines are more efficient in...
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It comprises 30 questions divided into two sections, with the final section being gamified.
75 MINUTE TEST aptitude, reasoning, coding
I applied via campus placement at Bengal Engineering College (BEC) and was interviewed before May 2023. There were 3 interview rounds.
It has logical, verbal, aptitude and programming
I applied via Approached by Company and was interviewed in Oct 2024. There were 2 interview rounds.
I applied via Company Website and was interviewed in Aug 2023. There was 1 interview round.
DRAM is volatile memory that stores data temporarily, while SRAM is faster and more expensive but retains data as long as power is supplied.
DRAM stands for Dynamic Random Access Memory, while SRAM stands for Static Random Access Memory.
DRAM requires refreshing to retain data, while SRAM does not.
DRAM is slower and less expensive than SRAM.
Examples of DRAM include DDR3 and DDR4, while examples of SRAM include L1, L2, an
I applied via Campus Placement and was interviewed in Aug 2022. There were 9 interview rounds.
For the bright future and for overall skill development these programs helps very much
For increasing and boost my knowledge these management program helps in achieving my career goals
For the bright future and for overall skill development these programs helps very much
For the bright future and for overall skill development these programs helps very much
For the bright future and for overall skill development these programs helps very much
There will be four and five students group discussion
I applied via Recruitment Consulltant and was interviewed in Jul 2022. There were 2 interview rounds.
Basic c datastructucture networking l2 l3 questions
Packets are sent from source to destination through a series of network devices using routing protocols.
Packet is created at the source with source and destination IP addresses.
Packet is sent to the default gateway or router.
Router checks its routing table to determine the next hop for the packet.
Packet is forwarded to the next hop until it reaches the destination.
Destination receives the packet and sends an acknowledg
To delete a node from a single linked list, we need to find the node and update the pointers.
Traverse the list to find the node to be deleted
Update the previous node's pointer to point to the next node
Free the memory of the node to be deleted
Dynamic memory allocation in C allows allocation of memory at runtime.
Dynamic memory allocation is done using functions like malloc(), calloc(), realloc() and free().
malloc() allocates memory block of specified size and returns a pointer to the first byte of allocated memory.
calloc() allocates memory block of specified size and initializes all bits to zero.
realloc() changes the size of previously allocated memory block...
Interprocess communication is a mechanism that allows processes to communicate with each other in an OS.
IPC mechanisms include pipes, sockets, message queues, shared memory, and signals.
IPC can be used for synchronization, data sharing, and coordination between processes.
IPC can be implemented using system calls such as fork(), pipe(), socket(), and msgget().
I applied via Naukri.com and was interviewed in Apr 2021. There were 4 interview rounds.
A watchdog timer is a hardware or software component that monitors the operation of a system and resets it if necessary.
A watchdog timer is used to prevent system crashes or lock-ups by resetting the system if it becomes unresponsive.
It is typically implemented as a counter that needs to be periodically reset by the system software.
If the watchdog timer is not reset within a certain time period, it triggers a system re...
Semaphore is a synchronization object used to control access to a shared resource.
Semaphore is a signaling mechanism used to control access to a shared resource
It allows multiple processes/threads to access the shared resource simultaneously
Semaphore maintains a count of the number of resources available
When a process/thread requests access to the resource, the count is decremented
When the process/thread releases the r...
Interrupt latency is the time delay between the occurrence of an interrupt and the start of the routine that services the interrupt.
Interrupt latency is a critical factor in real-time systems
It can be affected by factors such as the priority of the interrupt and the current state of the processor
Reducing interrupt latency can improve system performance and responsiveness
Examples of interrupts include hardware interrupt...
DMA address deals with data transfer between memory and peripherals without CPU intervention.
DMA stands for Direct Memory Access.
DMA address is used to transfer data between memory and peripherals without CPU intervention.
DMA address is used to reduce the load on the CPU and improve system performance.
Examples of peripherals that use DMA include network cards, sound cards, and hard drives.
Interview experience
Design & Verification Engineer
3
salaries
| ₹6 L/yr - ₹9 L/yr |
TCS
Accenture
Wipro
Cognizant