MosChip Technologies Physical Design Engineer Interview Questions and Answers

Q1. Floorplan strategies to calculate maximum macro counts that can be used in a block, placement constraints, congestion issues.
Ans. 
Floorplan strategies involve calculating maximum macro counts, considering placement constraints and addressing congestion issues.
• Floorplan strategies involve determining the maximum number of macros that can be accommodated within a block.

• Placement constraints refer to the rules and guidelines that dictate where macros can be placed within the block.

• Congestion issues arise when there is limited space or resources avai...read more
Answered by AI
Add your answer
Q2. Multi cycle paths, timing violations in reg2reg path.
Add your answer
Q3. Routing issues, signal integrity, IR drop analysis.
Add your answer
Q4. Logical DRC's, causes and fixing strategies.
Add your answer

Q1. Issues and fixes faced during previous projects.
Add your answer
Q2. Placement, CTS, CMOS concepts
Add your answer
Q3. LVS, Design for manufacturing.
Add your answer

Q1. Sv hvm questions on constraiants and assertions
Add your answer
Q2. Questions on resume projects
Add your answer

Q1. Questions on protocols
Add your answer
Q2. Sv uvm questions
Add your answer

Q1. Salary and pckge discussion
Add your answer
Q2. Details on client interview
Add your answer

Q1. Projects and challenges
Add your answer
Q2. Sv uvm basics
Add your answer

Q1. Toggle the bits of given input
Ans. 
Toggle the bits of given input
• Create a mask with all bits set to 1

• XOR the input with the mask to toggle the bits

• Repeat the process for each bit position
Answered by AI
Add your answer
Q2. Clear the set bit
Add your answer

Q1. Print the star pattern
Ans. 
Print a star pattern using loops
• Use nested loops to print the desired pattern

• Increment the number of stars in each row to create the pattern

• Example: for a pattern with 5 rows - * , ** , *** , **** , *****
Answered by AI
Add your answer
Q2. Microprocessor microcontroller topics are asked
Add your answer

Q1. Simple FSM given similar to mux and asked for testcases and assertions.
Add your answer
Q2. Coverage to write transitions of states.
Ans. 
Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.
• Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.

• Writing directed tests to cover specific state transitions can help achieve higher coverage.

• Random stimulus generation can also be used to explore different state transitions.

• Functional coverage can...read more
Answered by AI
Add your answer

Q1. Basics of analog , digital and vlsi
Add your answer
Q2. On face to face interview, they asked me abt my projects , digital, little analog , vlsi ( verilog), microcontrollers and c programming
Add your answer

40 aptitude qns and some mcqs on basic programming

Q1. I was asked to write two sum, palindrome function and merge sort code in whatever language I'm comfortable in
Add your answer
Q2. Two sum- return true or false
Ans. 
Given an array of integers, determine if there are two numbers that add up to a specific target.
• Iterate through the array and store each element in a hash set.

• For each element, check if the difference between the target and the element exists in the hash set.

• If the difference exists, return true; otherwise, continue iterating.

• Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.
Answered by AI
View 1 more answer
Q3. Merge sort function code
Add your answer
Q4. Palindromic string or not
Add your answer

Q1. Asked the working experience and the related skills to the new job
Add your answer

Q1. Coding questions in Verilog, Systemverilog, random constraints such as how to write a onehot in different ways
Add your answer

Q1. Asked the expectation of the base salary and overall compensation
Add your answer

Q1. Sdc basics TCL coding
Add your answer