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I applied via LinkedIn and was interviewed in Jul 2024. There was 1 interview round.
FPGAs are Field-Programmable Gate Arrays used in hardware design. They can be categorized as SRAM-based, Flash-based, or Antifuse-based.
SRAM-based FPGAs are volatile and require reprogramming every time they power up. Examples include Xilinx Virtex series.
Flash-based FPGAs are non-volatile and retain their configuration even when powered off. Examples include Actel ProASIC3 series.
Antifuse-based FPGAs are OTP (One-Time...
Decoupling analysis involves calculating the required capacitance to maintain stable voltage levels in a circuit.
Decoupling analysis is essential for ensuring stable power supply in electronic circuits.
It involves calculating the amount of capacitance needed to filter out noise and maintain voltage levels.
Decoupling capacitors are placed strategically in a circuit to provide this filtering effect.
The formula for calcul...
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I applied via campus placement at PSG College of Technology, Coimbatore and was interviewed in Jul 2024. There were 3 interview rounds.
It consisted of aptitude questions, then OS C 1mrks, which were re GATE questions. No coding, I chose hardware role, so questions were from digital electronics too. prepare the gate questions for these subjects
I was interviewed in Jun 2024.
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Jun 2024. There were 2 interview rounds.
Basic ece ques and apti
Flip flops and latches are sequential logic circuits used in digital electronics to store and transfer data.
Flip flops are clocked circuits that store one bit of data, while latches are level-sensitive circuits that store data as long as the enable signal is active.
Flip flops are edge-triggered, meaning they change state on a clock edge, while latches are level-triggered, changing state as long as the enable signal is ...
Was asked details of scanning electron microscopy
Aptitude, Digital Electronics.
Questions on dgital electronics and circuits
posted on 28 Aug 2022
I applied via Campus Placement and was interviewed in Jul 2022. There were 2 interview rounds.
Digital Electronics, verilog basics,C language basics,
Designing a digital system for detecting start bit in UART communication
The start bit is the first bit in a UART transmission and is always a logic low
The system should sample the incoming data at a rate higher than the baud rate to accurately detect the start bit
A shift register can be used to store the incoming data and detect the start bit
The system should also check for framing errors and parity errors
I applied via Campus Placement and was interviewed in Apr 2024. There were 3 interview rounds.
Basic apptitude and digital and analog mcqs
Use a 4:1 mux to create a 3 input XOR gate.
Connect two of the inputs to the select lines of the mux.
Connect the third input to one of the data inputs of the mux.
Connect the other data input of the mux to the output of an XOR gate between the first two inputs.
Use the output of the mux as the output of the 3 input XOR gate.
I applied via Campus Placement and was interviewed in Sep 2023. There were 2 interview rounds.
In this round Aptitude questions related to unitary method, probability and others were asked. In technical Test questions of Digital Electronics and Analog Electronics were asked.
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