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posted on 9 Apr 2022
I applied via Campus Placement and was interviewed before Apr 2021. There was 1 interview round.
UVM has 4 phases: build, connect, run, and cleanup. Reg is a hardware component, logic is a design component.
UVM phases are build, connect, run, and cleanup
Build phase creates the test environment
Connect phase connects the testbench to the design
Run phase executes the test
Cleanup phase destroys the test environment
Reg is a hardware component that stores data
Logic is a design component that performs operations on data
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posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
posted on 15 Jan 2025
posted on 29 Aug 2024
UVM (Universal Verification Methodology) basic principle is to provide a standardized methodology for verifying digital designs.
UVM is based on SystemVerilog and provides a framework for creating reusable verification environments
It promotes the use of object-oriented programming techniques for creating modular and scalable testbenches
UVM encourages the use of constrained-random stimulus generation and coverage-driven ...
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
posted on 5 Apr 2024
posted on 29 Apr 2024
I applied via campus placement at Indian Institute of Technology (IIT), Kharagpur and was interviewed before Apr 2023. There were 2 interview rounds.
I plan to continue advancing my skills in design verification engineering and eventually move into a leadership role.
Continue taking relevant courses and certifications to stay updated on industry trends
Seek opportunities to lead projects and teams to gain leadership experience
Network with professionals in the field to learn from their experiences and insights
posted on 27 Sep 2022
I applied via Company Website and was interviewed in Mar 2022. There were 3 interview rounds.
Had basic aptitude questions, verilog , c programming, digital electronics, analog electronics,computer architecture.
posted on 7 May 2024
I applied via Referral and was interviewed in Apr 2024. There was 1 interview round.
Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.
Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.
Writing directed tests to cover specific state transitions can help achieve higher coverage.
Random stimulus generation can also be used to explore different state transitions.
Functional coverage can...
posted on 23 Nov 2022
Verilog, c++ pointers, mosfets
UART protocol can be used to transmit and receive data between two devices.
UART can be used to communicate between a microcontroller and a computer
UART can be used to send and receive data between two microcontrollers
UART can be used to interface with sensors and actuators
UART can be used to implement a simple command/response protocol
UART can be used to implement a data logging system
UART can be used to receive signals from a microcontroller.
Connect the UART pins of the microcontroller to the UART pins of the receiving device.
Configure the UART settings such as baud rate, parity, and stop bits.
Use a UART library or write code to read the incoming data from the UART buffer.
Process the received data as required by the application.
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