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I applied via LinkedIn and was interviewed in Dec 2023. There was 1 interview round.
Sync reset is synchronized with clock signal while async reset is not synchronized.
Sync reset is asserted/deasserted at a specific clock edge
Async reset is independent of clock signal
Sync reset is used in sequential circuits like flip-flops
Async reset is used in combinational circuits like logic gates
The random function generates a random number within a specified range.
The random function is commonly used in programming to introduce randomness into a program.
It can be used to simulate unpredictable events or generate random data for testing purposes.
I applied via Campus Placement
Designed a smart irrigation system using IoT technology for Btech final project.
Implemented sensors to measure soil moisture levels
Utilized microcontrollers to control water flow based on sensor data
Developed a mobile app for remote monitoring and control
I applied via Campus Placement and was interviewed before Feb 2023. There were 3 interview rounds.
What people are saying about Intel
posted on 8 Jul 2024
MB cells advantage lies in their ability to provide high accuracy and efficiency in post silicon validation testing.
MB cells offer high accuracy in detecting defects in silicon chips
They provide efficient testing solutions for post silicon validation
MB cells help in identifying and resolving issues in the design and manufacturing process
posted on 29 Nov 2024
Toggle the bits of given input
Create a mask with all bits set to 1
XOR the input with the mask to toggle the bits
Repeat the process for each bit position
Print a star pattern using loops
Use nested loops to print the desired pattern
Increment the number of stars in each row to create the pattern
Example: for a pattern with 5 rows - * , ** , *** , **** , *****
posted on 2 Oct 2024
I applied via campus placement at Netaji Subhas Institute of Technology (NSIT) and was interviewed in Sep 2024. There were 2 interview rounds.
Basic aptitude-10 question,digital moderate -Question,analog moderate -10 question,verilog and system verilog -10 question
Cross talk is the unwanted transfer of signals between different components or traces on a circuit board.
Occurs when signals from one trace interfere with signals on another trace
Can lead to signal distortion or errors in data transmission
Prevented by proper spacing and shielding between traces
Example: Cross talk between data lines on a PCB causing errors in communication
Generated clocks through edges are defined by specifying the source clock and the edge on which the generated clock is based.
Specify the source clock for the generated clock
Define the edge (rising/falling) on which the generated clock is based
Use tools like Synopsys Design Compiler to define generated clocks
posted on 7 May 2024
I applied via Referral and was interviewed in Apr 2024. There was 1 interview round.
Coverage-driven verification techniques are used to ensure all possible state transitions are exercised.
Coverage metrics like state, transition, and toggle coverage can be used to track the completeness of state transitions.
Writing directed tests to cover specific state transitions can help achieve higher coverage.
Random stimulus generation can also be used to explore different state transitions.
Functional coverage can...
posted on 29 Feb 2024
I applied via Campus Placement and was interviewed in Jan 2024. There was 1 interview round.
I applied via LinkedIn and was interviewed in Oct 2023. There were 2 interview rounds.
40 aptitude qns and some mcqs on basic programming
Given an array of integers, determine if there are two numbers that add up to a specific target.
Iterate through the array and store each element in a hash set.
For each element, check if the difference between the target and the element exists in the hash set.
If the difference exists, return true; otherwise, continue iterating.
Example: nums = [2, 7, 11, 15], target = 9. The function should return true as 2 + 7 = 9.
based on 3 interviews
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