Appasamy Associates Fpga Design Engineer Interview Questions and Answers

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Q1. Try to have good knowledge on subject
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Q2. Difference between task and function in verilog
Ans. 
Task and function are subprograms in Verilog used for code modularity and reusability.
• Functions return a value while tasks do not.

• Functions can be called from expressions while tasks cannot.

• Tasks can have delays and event controls while functions cannot.

• Functions can have multiple return statements while tasks cannot.

• Functions can have input and output arguments while tasks can only have input arguments.
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