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Jagruti Technosys Asic Design Verification Engineer salaries in India

Annual salary range
1 - 2 years exp.
₹1.2 Lakh - ₹2.8 Lakhs
Salary of majority employees
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81% less than the average Asic Design Verification Engineer Salary for 1 - 2 years of experience

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Salaries in different departments

Engineering - Hardware & Networks
Asic Design Verification Engineer Salary
1 - 2 years exp. (AmbitionBox Estimate)
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₹2.4 L/yr - ₹2.8 L/yr

Engineering - Software & QA
Asic Design Verification Engineer Salary
1 year exp. (AmbitionBox Estimate)
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₹1.2 L/yr - ₹1.5 L/yr

Last Updated: 14 Mar 2023

Companies similar to Jagruti Technosys for Asic Design Verification Engineer

Company name Avg Annual Salary Open Jobs
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₹4 L/yr - ₹10.9 L/yr

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1 job opening
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₹13 L/yr - ₹20 L/yr

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TCS Asic Design Verification Engineer Salary

2 - 3 years exp. (3 salaries)

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₹3.2 L/yr - ₹4.3 L/yr

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₹1.5 L/yr - ₹5 L/yr

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₹3 L/yr - ₹6 L/yr

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Asic Design Verification Engineer salary at Jagruti Technosys ranges between ₹1.2 Lakh to ₹2.8 Lakhs per year for employees with experience between 1 year to 2 years. Salary estimates are based on 4 latest salaries received from various employees of Jagruti Technosys.

Latest annual salaries shared by Jagruti Technosys Asic Design Verification Engineer

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1 year exp.
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2 years exp.
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1 year exp.
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1 year exp.

Experience wise Jagruti Technosys Asic Design Verification Engineer salaries

Last Updated: 14 Mar 2023

Experience Avg Annual Salary
1 year  (3 salaries)

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₹1.2 L/yr - ₹2.8 L/yr
2 years (AmbitionBox Estimate)

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₹2.2 L/yr - ₹2.8 L/yr

Similar Designation salaries in Jagruti Technosys

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₹1.9 L/yr - ₹4.8 L/yr
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₹2.05 L/yr - ₹2.2 L/yr
Embedded Trainee Engineer Salary
(AmbitionBox Estimate)
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₹1.6 L/yr - ₹2.1 L/yr
Embedded Engineer Salary
(AmbitionBox Estimate)
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₹3 L/yr - ₹3.8 L/yr
Embedded Software Engineer Salary
(AmbitionBox Estimate)
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₹1.7 L/yr - ₹2.2 L/yr
Embedded Software Developer Salary
(AmbitionBox Estimate)
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₹1.3 L/yr - ₹1.6 L/yr

Salary related reviews for Jagruti Technosys

Engineering - Software & QA Department

5.0
  •  posted on 16 Aug 2020

4.0
 for  Salary and Benefits

Likes

Jagruti Technosys is the best company for freshers because the senior PD Engineers are very kind and helpful and so the Team Leads are . Jagruti believes in every employee and open to any ideas came up by employees and also gives them the credit.

read more

Dislikes

There is nothing to dislike about Jagruti Technosys except for Job security.

Research & Development Department

4.0
  •  posted on 05 Jun 2018

3.0
 for  Salary and Benefits

Likes

I'm so glad that I have received to write a feedback about Jagruti.It is one of the most pleasurable moment working at Jagruti. The most exciting part here is people around me are so encouraging and gives me a lot of strength to work very hard. We at Jagruti work with passion towards a particular objective. We have fun and make our environment so funny everyday. We smile all the day so that we can also be healthy.

read more

Dislikes

We work as a embedded trainee. There is no growth and pay is low.

see more salary related reviews

Jagruti Technosys Asic Design Verification Engineer Salary FAQs

What is the salary of Asic Design Verification Engineer at Jagruti Technosys?
Asic Design Verification Engineer salary at Jagruti Technosys in India ranges between ₹1.2 Lakhs to ₹2.8 Lakhs for experience between 1 years to 2 years. According to our estimates it is 81% less than the average Asic Design Verification Engineer Salary in India. Salary estimates are based on 4 latest salaries received from various employees of Jagruti Technosys India.
How does the salary of a Asic Design Verification Engineer at Jagruti Technosys India compare with the average salary range for this job?
The average salary of a Asic Design Verification Engineer at Jagruti Technosys is 81% less than the average salary of a Asic Design Verification Engineer in India. To know exact salary insights, login to view.
Which similar companies are paying more than Jagruti Technosys to a Asic Design Verification Engineer in India?
  • Tech Mahindra Asic Design Verification Engineer Salary - ₹13.0 Lakhs to ₹20.0 Lakhs per year
  • Wipro Asic Design Verification Engineer Salary - ₹4.0 Lakhs to ₹10.9 Lakhs per year
  • Eximius Design Asic Design Verification Engineer Salary - ₹3.0 Lakhs to ₹6.0 Lakhs per year
  • TCS Asic Design Verification Engineer Salary - ₹3.2 Lakhs to ₹4.3 Lakhs per year
  • RiseTime Semiconductors Asic Design Verification Engineer Salary - ₹1.5 Lakhs to ₹5.0 Lakhs per year
What is the estimated take home salary of a Asic Design Verification Engineer at Jagruti Technosys in India?
The estimated take-home salary of a Asic Design Verification Engineer at Jagruti Technosys ranges between ₹13,492 per month to ₹14,929 per month in India. The take-home salary calculation is based on the average Jagruti Technosys Asic Design Verification Engineer salary in India which ranges between ₹1.2 Lakhs to ₹2.8 Lakhs per year for employees with experience between 1 years to 2 years. Check how did we calculate take home salary?

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Jagruti Technosys Asic Design Verification Engineer salary in India ranges between ₹1.2 Lakh to ₹2.8 Lakhs with an average annual salary of ₹unlock blur. Salary estimates are based on 4 Jagruti Technosys latest salaries received from various employees of Jagruti Technosys.