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Siemens EDA
4.4
based on 44 Reviews
Company Overview
Company Locations
Working at Siemens EDA
Company Summary
Overall Rating
4.4/5
based on 44 reviews
Highly rated for
Company culture, Job security, Work-life balance
Work Policy
Hybrid
87% employees reported
Monday to Friday
100% employees reported
Flexible timing
93% employees reported
No travel
82% employees reported
View detailed work policy
Top Employees Benefits
Free meal
6 employees reported
Office gym
6 employees reported
Cafeteria
6 employees reported
Health insurance
6 employees reported
View all benefits
About Siemens EDA
Founded in--
India Employee Count--
Global Employee Count--
Headquarters--
Office Locations
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Websiteeda.sw.siemens.com
Primary Industry
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Other Industries
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Siemens EDA Ratings
based on 44 reviews
Overall Rating
4.4/5
How AmbitionBox ratings work?
5
24
4
16
3
3
2
0
1
1
Category Ratings
4.4
Company culture
4.4
Job security
4.4
Work-life balance
4.0
Salary
4.0
Work satisfaction
3.9
Promotions
3.8
Skill development
Siemens EDA is rated 4.4 out of 5 stars on AmbitionBox, based on 44 company reviews. This rating reflects a generally positive employee experience, indicating satisfaction with the company’s work culture, benefits, and career growth opportunities. AmbitionBox gathers authentic employee reviews and ratings, making it a trusted platform for job seekers and employees in India.
Read more
Gender Based Ratings at Siemens EDA
based on 40 reviews
4.5
Rated by 9 Women
Rated 4.5 for Work-life balance and 4.3 for Company culture
4.4
Rated by 31 Men
Rated 4.5 for Job security and 4.4 for Work-life balance
Work Policy at Siemens EDA
based on 15 reviews in last 6 months
Hybrid
87%
Work from office
13%
Siemens EDA Reviews
Top mentions in Siemens EDA Reviews
Compare Siemens EDA with Similar Companies
Change Company | Change Company | Change Company | ||
|---|---|---|---|---|
Overall Rating | 4.4/5 based on 44 reviews | 3.7/5 based on 92.1k reviews | 3.7/5 based on 54.4k reviews | 3.8/5 based on 58.2k reviews |
Highly Rated for | Work-life balance Job security Company culture | Job security Work-life balance | Job security | No highly rated category |
Critically Rated for | No critically rated category | Promotions Salary Work satisfaction | Promotions Salary | Promotions |
Primary Work Policy | Hybrid 87% employees reported | Work from office 81% employees reported | Hybrid 61% employees reported | Hybrid 75% employees reported |
Rating by Women Employees | 4.5 Good rated by 9 women | 3.7 Good rated by 26.8k women | 3.8 Good rated by 15.6k women | 3.8 Good rated by 21.9k women |
Rating by Men Employees | 4.4 Good rated by 31 men | 3.6 Good rated by 60.2k men | 3.7 Good rated by 36.3k men | 3.8 Good rated by 33.7k men |
Job security | 4.4 Good | 4.5 Good | 3.8 Good | 3.7 Good |
View more
Siemens EDA Salaries
Siemens EDA salaries have received with an average score of 4.0 out of 5 by 44 employees.
Senior Member of Technical Staff
(44 salaries)
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₹15 L/yr - ₹28 L/yr
Member Technical Staff
(19 salaries)
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₹13.6 L/yr - ₹21 L/yr
Technical Staff Member Lead
(15 salaries)
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₹22.1 L/yr - ₹33.5 L/yr
Senior Technical Staff Member
(11 salaries)
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₹15.2 L/yr - ₹21 L/yr
Software Developer
(8 salaries)
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₹12 L/yr - ₹23 L/yr
Software Engineer
(7 salaries)
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₹10 L/yr - ₹22 L/yr
Associate Lead Engineer
(7 salaries)
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₹18 L/yr - ₹30 L/yr
QA Engineer
(5 salaries)
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₹10 L/yr - ₹12.5 L/yr
Lead Member Technical Staff
(5 salaries)
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₹24 L/yr - ₹30 L/yr
Senior Full Stack Developer
(5 salaries)
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₹30.8 L/yr - ₹35.5 L/yr
Siemens EDA News
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Taking 3D IC Heterogeneous Integration Mainstream
- 3D IC heterogeneous integration, a system approach, disaggregates what would be implemented as an SoC into chiplets for improved performance at reduced cost and higher yield.
- System Technology Co-optimization (STCO) involves architectural planning, analysis, physical design, and electrical and reliability analysis in 3D IC design.
- The Chiplet Design Exchange (CDX) established within the Open Compute Project aims to promote 3D IC technology and create a chiplet ecosystem.
- The CDX group consists of EDA vendors, FABs, OSATs, and substrate material providers working on design kits for 3D IC integration.
- To support 3D IC design, four 3DKs are being developed: Chiplet Design Kits (CDK), Package Assembly Design Kits (PADK), Material Design Kits (MDK), and Package Test Design Kits (PTDK).
- CDK models are recommended for early planning and design, while PADK defines pitch spacing rules and material properties are defined by MDKs.
- MDKs provide material properties for thermal, stress, and signal integrity analysis, while PTDKs define test IO pins and functions.
- The 3DK models enable chiplet ecosystem development, allowing chiplet suppliers to describe their products and enable designers to choose suitable parts.
- The CDX group is working on authoring tools to create 3DK models in a machine-readable, open-source EDA-neutral format to propel 3D IC integration into mainstream design.
- Innovator3D IC by Siemens EDA offers a multi-physics cockpit for 3D IC design and manufacturing, facilitating planning and heterogeneous integration of ASICs and chiplets.
3Dincites | 26 Mar, 2025
Simplifying HW/SW Co-Verification With PSS Led UVM And C Tests
- Hardware and software co-verification is crucial for validating SoC designs amidst growing complexities in system on chips (SoCs).
- Traditionally, early testing is done using UVM for creating reusable verification components before transitioning to software-driven tests in C.
- The Portable Test and Stimulus Standard (PSS) addresses the need to reuse verification intent across diverse implementations.
- Integrating PSS, UVM, and C++ offers significant benefits for HW/SW co-verification in SoC designs.
- The proposed methodology involves developing PSS models, debugging, adding exec block contents for C and UVM tests, and integrating tests into UVM test bench.
- This approach streamlines verification processes by enhancing automation, abstraction, and quality of SoC designs.
- The use of PSS, UVM, and C++ enables versatile testbench development, leveraging object-oriented programming for complexity management and maintainability.
- This methodology facilitates HW/SW co-verification, allowing verification engineers to cover various aspects efficiently.
- The integration of PSS, UVM, and C++ aims to enhance the reliability and quality of SoC designs by streamlining the verification process.
- Siemens EDA's paper 'A novel approach for HW/SW co-verification: Leveraging PSS to orchestrate UVM and C tests' provides detailed insights on improving co-verification techniques.
- Key contributors to this methodology include professionals from Siemens EDA with expertise in simulation products, verification methodologies, and product engineering.
Semiengineering | 27 Feb, 2025
Chip Industry Week In Review
- Worldwide silicon wafer shipments declined nearly 2.7% to 12,266 million square inches in 2024, with wafer revenue contracting 6.5% to $11.5 billion.
- CSIS released a new report focusing on building a secure mineral supply chain for semiconductors, particularly in refining gallium and germanium.
- Europe is investing significantly in AI infrastructure projects, with France announcing over €109 billion in investments and the EU Commission launching InvestAI initiative.
- Advantest introduced an ultra-high-speed DRAM test system for GDDR7, LPDDR6, and DDR6 applications in AI, HPC, and edge technologies.
- Synopsys expanded its hardware-assisted verification portfolio with new prototyping and emulation systems based on AMD's Versal adaptive SoC.
- Semiconductor Engineering delved into topics like signal integrity in chiplet design and multi-physics in the Low Power-High Performance newsletter.
- Lam Research, TSMC, and other companies in Asia and Europe made notable investments and collaborations in the semiconductor industry.
- NXP plans to acquire Kinara, Groq secures a $1.5 billion commitment, and other companies like EnCharge AI and Salience Labs receive significant funding.
- Yole Group and TrendForce provided insights on the semiconductor and AI server markets, with expectations of strong growth rates and challenges for 2025.
- Google Cloud shared solutions for power spikes in AI workloads, while advancements in quantum computing and supercomputing were also highlighted.
- Companies like Nordson, Siemens EDA, Infineon, and Ansys announced new products, collaborations, and achievements in various technology sectors.
Semiengineering | 14 Feb, 2025
Silent Data Errors Still Slipping Through The Cracks
- Silent data corruption errors in large server farms have become a major concern of cloud users, hyperscalers, processor manufacturers and the test community.
- Silent data errors (also called silent data corruption errors) are hardware errors that occur when an incorrect computational result from a processor core goes undetected by the system.
- Silent data errors are not a new type of failure or caused by a new type of defect, but they are more noticeable.
- Both Google and Meta sounded the alarm about SDC errors a few years ago, and the extent of the problem boils down to 1 in 1,000 machines in a data center fleet having a silent data error.
- These silent data errors also have become more prevalent due to ever-shrinking transistors fabricated near their physical limits, huge numbers of cores in data centers running identical code, and the limitations in testing hugely complex systems.
- Effective screening and testing can help to detect SDCs, both during fabrication and during field use.
- Stress testing is a powerful play here.
- Systems are likely to get more complex, so one key in dealing with SDEs may lie in developing more fault-tolerant systems with superior error correction mechanisms and built-in resiliency.
- ‘In the future, we’re going to be talking about reliability as a first-class design parameter in architectures,’ said Rambus’ Woo.
- And while it’s not clear that the industry will unravel all the root cause contributors to silent data errors, strategies to identify, check/verify, diagnose and test for SDEs are well underway.
Semiengineering | 11 Feb, 2025
Automotive Security Shifts To The System Level
- As the amount of semiconductor and software content continues to increase, so does the number of over-the-air updates and connections to edge-based servers and services, adding a variety of new vectors for attacks.
- Properly securing vehicles requires engineers to first identify all the possible connection points.
- In the strictest sense, there’s only one direct attack vector on a car, according to David Glasco, vice president for compute solutions group at Cadence — the WiFi through which all software updates are uploaded.
- The migration toward holistic security now includes roots of trust installed in ICs located throughout the car’s systems.
- “Security is just like safety,” he said. “Security is the ultimate. It is the top priority.
- The challenge for automakers is understanding how these systems of systems will behave both individually and together, and that may require security training as a pre-requisite for any facet of automotive design.
- SDVs are booming, but designing hardware that can run software updates a decade in the future is a huge challenge.
- The core of all security comes down to proper, strong cryptography.
- “Having multiple environments is very similar to having different privilege levels within the CPU structure, which allows you to assign a very low privilege, for example, to a third-party app,” he said.
- The international standard has been proven effective in automotive functional safety and has begun to spread to other markets.
Semiengineering | 6 Feb, 2025
Automotive Outlook 2025: Ecosystem Pivots Around SDV
- The automotive industry is shifting towards the software-defined vehicle architectures (SDV) that will change how automakers design, source, and use automotive chips.
- SDV provides various benefits to automakers because it can reduce manufacturing costs, upgrade the operational platform quickly, support scalability and flexibility, and deliver advanced user experience.
- SDV requires software-first development and a shift from the mechanical and hardware-centric point of view to software-centralized infrastructure that can build and integrate the hardware accordingly.
- This shift involves creating a zonal architecture with powerful central CPUs to consolidate electronic control units (ECUs) into fewer, more powerful platforms that centralize processing resources in vehicles.
- The zonal architecture enables the integration of advanced technologies such as AI and autonomous driving systems, and it simplifies the vehicle design process while reducing complexity, weight, and cost.
- Chip vendors are building multi-die licensable devices featuring multiple chips in a single package, allowing the creation of advanced products using advanced packages at 3nm and a range of chiplets from different vendors.
- SDV enhances AI use in the vehicle, delivering an advanced user experience that learns from driver behaviors and enhances automated driving systems with end-to-end self-supervised learning and advanced AI in the vehicle.
- Software-defined development speeds up the introduction of new technologies that OEMs and Tier Ones are embracing. However, OEMs and Tier Ones must adapt to software-first development with a focus on security since the distribution of software centrally intensifies security issues.
- SDV makes it possible to develop software independently within the cloud on servers and substantially reduces the development time and cost with a level of flexibility and scalability that traditional hardware development cannot match.
- Virtual platforms and virtual prototypes are accelerating the software and silicon development cycles, simultaneously designing the hardware and software, testing them for security, scalability, flocking everything together into a scalable E/E architecture for the whole car.
Semiengineering | 6 Feb, 2025
Enhancing Reliability For Automotive ICs
- Reliability is a top priority for IC designers as automotive ICs must withstand extreme conditions and meet rigorous industry standards.
- Traditional design approaches that rely heavily on simulation and late-stage validation are no longer sufficient.
- Shifting left is a methodology that addresses potential issues as early as possible in the design flow.
- Design analysis tools can play a transformative role in identifying and mitigating reliability risks upfront.
- Insight Analyzer from Siemens EDA offers a comprehensive set of reliability-focused analysis capabilities that go beyond traditional simulation and electrical rule checking.
- Advanced algorithms offer deeper insights into the implicit performance and reliability characteristics of designs before committing to a full-blown simulation.
- Incorporating pre-layout design analysis using a tool like Insight Analyzer can streamline workflows and help deliver more reliable and robust automotive ICs.
- The shift-left approach empowers designers to deliver automotive ICs that are inherently more reliable and resilient.
- Automotive ICs are under unique reliability demands as they must operate under extreme temperatures and vibrations.
- Incorporating specialized design analysis tools can enable proactive identification of reliability concerns
Semiengineering | 6 Feb, 2025
Blog Review: Oct. 30
- Hardware-assisted verification techniques like emulation and prototyping are essential for improving design behavior.
- Ultra high-density interconnect (UHDI) is changing PCB design and production, enabling high-density circuitry.
- Automating PCB documentation generation reduces time and effort invested in developing and maintaining multiple documents.
- Root causes of errors in electrostatic discharge (ESD) verification are explored, highlighting factors that can yield incorrect resistances.
Semiengineering | 30 Oct, 2024
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Siemens EDA FAQs
Does Siemens EDA have good work-life balance?
Siemens EDA has a work-life balance rating of 4.4 out of 5 based on 40+ employee reviews on AmbitionBox. 91% employees rated Siemens EDA 4 or above on work-life balance. This rating reflects the company's efforts to help employees maintain a healthy balance between their personal and professional lives. We encourage you to read Siemens EDA work-life balance reviews for more details
Is Siemens EDA good for career growth?
Career growth at Siemens EDA is rated fairly well, with a promotions and appraisal rating of 3.9. 91% employees rated Siemens EDA 4 or above, while 9% employees rated it 3 or below on promotions/appraisal. Though the sentiment is mixed for career growth, majority employees have rated it positively. We recommend reading Siemens EDA reviews for more detailed insights.
What are the pros of working in Siemens EDA?
Working at Siemens EDA offers several advantages that make it an appealing place for employees. The company is highly rated for company culture, job security and work life balance, based on 40+ employee reviews on AmbitionBox.
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