Wipro - ASIC RTL Design - Bengaluru, Hyderabad, Pune, Noida, Kochi

Greetings from Wipro 😊

Hope you are doing great 😊

We have couple of exciting roles, please find the below active JD & share us your updated resume highlighting the Mandary skills in your profile

Email - swetha.janardhan@wipro.com

Requirement Name : ASIC RTL Design(IP RTL design targeted for SOC, Static checks, protocols)

Job Type : Full Time with Wipro

Exp : 3 Years 25 Years

Work Location Bengaluru, Hyderabad, Pune, Noida, Kochi

Notice : Immediate 30 days

Role Senior Engineer / Technical Lead / Architect / Technical Manager (Individual Contributor & Managing a Team)

Kindly refer or circulate this opportunity with your colleagues /friends who are seeking for challenging role.

Exp in ASIC RTL Design (Please mention in years):

Exp in IP (Please mention in years):

Exp in RTL Development (Please mention in years):

Exp in RTL design targeted for SOC, (Please mention in years):

Exp in Static checks (Please mention in years):

Exp in Protocols (Please mention in years):

Handons skills :

Name :

Total Exp :

Exp in ASIC RTL :

Notice Period & Negotiable :

LWD :

Holding Any Offer CTC:

Current Fixed CTC :

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Current Company Name :

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Reason for the new opportunity

JD:

JD of Senior ASIC/SoC RTL Engineer/Lead 4-15yrs
1) Expertise in SoC subsystem/IP design
2) Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
3) In depth knowledge on RTL quality checks (Lint, CDC)
4) Knowledge of synthesis and low power is a plus
5) Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
6) Good understanding of timing concepts
7) Knowledge of one or more of the interface protocols
a. PCIe
b. DDR
c. Ethernet
d. I2C, UART, SPI
8) Expertise in setting up and using tools like
a. Spyglass Lint/CDC
b. Synopsys DC
c. Verdi/Xcellium
9) Understanding of scripting languages like Make flow, Perl ,shell, python etc
10) Understanding of processor architecture and/or ARM debug architecture is a plus
11) Able to help and debug issues for multiple subsystems
12) Able to create/review design documents for multiple subsystems
13) Able to support physical design, verification, DFT and SW teams on design queries and reviews

Thanks & Regards

Sweta

Assistant Manager - Talent Acquisition - Wipro

swetha.janardhan@wipro.com

linkedin.com/in/swetha-janardhan-7bb082119

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