R&D Engineering, Sr Staff Engineer

• The candidate would be part of the VIP group responsible for development of Verification IPs.
• Core responsibilities would include Designing and developing the VIP/Test-bench, Creating Verification plans, Coding sequences/Test-scenarios, Coverage driven verification.
• The responsibility would also include enhancement of the existing Verification IP products and interface with customers during VIP deployment.
• This is an opportunity to work with best in class verification, debug tools, Design IP & close collaboration with best protocol experts in the industry.
• You will work with highly professional and motivated colleagues who value and support your contribution.

Requirements:

• Bachelors/Masters with good academic record.
• 7+ years experience in developing HVL based verification environments, preferably using System Verilog.
• Exposure to coverage driven verification. Experience in verification methodologies like UVM/OVM.
• Exposure to complex SV test benches involving multiple protocols and VIPs.
• Experience in VIP development is highly desirable.
• Should have a strong work exposure on any of the industry standard protocols like PCIe, USB, Ethernet, MIPI etc.
• Demonstrates good analysis and problem-solving skills.
• Have a strong passion for work and driving things to closure.
• Leadership qualities to motivate and align team members towards business goals and priorities.
• As a motivator/leader of the R&D team in Synopsys, you will be responsible for Development and enhancements of features, flows and solutions Quality execution of VIP development, taking responsibility for designing, developing, debugging, creation of reliable plans and effort estimates for your projects. Focus on innovation to ensure continuous product enhancements