Upload Button Icon Add office photos
Engaged Employer

i

This company page is being actively managed by Synopsys Team. If you also belong to the team, you can get access from here

Synopsys Verified Tick

Compare button icon Compare button icon Compare
3.9

based on 331 Reviews

filter salaries All Filters

238 Synopsys Jobs

Senior FV Engineering Manager

5-9 years

Bangalore / Bengaluru

1 vacancy

Senior FV Engineering Manager

Synopsys

posted 5hr ago

Job Role Insights

Flexible timing

Job Description

We Are: At Synopsys, we drive the innovations that shape the way we live and connect.
Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines.
We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content.
Join us to transform the future through continuous technological innovation.
You Are: You are a seasoned verification professional with a passion for leading and mentoring teams.
You possess a deep understanding of formal verification methodologies and have a proven track record in managing complex verification projects.
Your excellent interpersonal and communication skills enable you to effectively collaborate with cross-functional teams and drive projects to successful completion.
You are proactive in identifying and addressing verification challenges and are always on the lookout for innovative ways to enhance verification efficiency and coverage.
With your extensive experience in digital design and verification, you are well-versed in high-speed interconnect protocols and industry-standard formal verification tools.
What Youll Be Doing: Lead, mentor, and grow a team of formal verification engineers, providing technical guidance, career development, and performance management to ensure a high-performing and engaged team.
Develop and drive the formal verification plans, aligning with project timelines and IP deliverables.
Define test plans tailored to high-complexity digital IPs, including CXL, UCIe, USB, and other interconnect protocols.
Manage multiple verification projects concurrently, coordinating with design, RTL, and DV teams.
Ensure verification goals, timelines, and milestones are met while maintaining quality standards.
Identify and implement state-of-the-art formal verification methodologies and tools, including assertions, SystemVerilog Assertions (SVA), and custom verification environments.
Drive innovation to enhance verification efficiency and coverage.
Evaluate and mitigate verification risks early in the design phase, ensuring that IPs meet high-quality standards and are thoroughly verified before release.
Collaborate with senior management on matters concerning several functional areas, divisions, and/or customers to drive verification strategies and ensure alignment with broader business objectives.
The Impact You Will Have: Ensure the successful verification of complex digital IPs, contributing to the delivery of high-quality products to our customers.
Enhance the efficiency and coverage of verification processes through the implementation of innovative methodologies and tools.
Build and maintain a high-performing verification team through effective leadership, mentorship, and career development.
Drive the alignment of verification plans with project timelines and IP deliverables, ensuring timely and successful project completion.
Mitigate verification risks early in the design phase, reducing the likelihood of costly design errors and rework.
Collaborate with cross-functional teams to ensure a cohesive and integrated approach to verification, design, and development.
What Youll Need: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field.
Advanced degrees preferred.
X+ years of experience in formal verification of digital design IPs, with a strong track record in verifying complex IPs.
Proven experience in managing and leading teams, with excellent interpersonal and communication skills.
Deep understanding of formal verification methodologies, including property-based and equivalence checking, SystemVerilog Assertions (SVA), and protocol compliance.
Strong familiarity with industry-standard formal verification tools, such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa Formal.
Extensive experience in digital design and verification for high-speed interconnect protocols.
Excellent problem-solving abilities and a proactive approach to identifying and addressing verification challenges.
Who You Are: A natural leader who inspires and motivates their team to achieve excellence.
An excellent communicator who can effectively convey complex technical concepts to diverse audiences.
A proactive problem solver who takes initiative to address challenges and implement solutions.
A collaborative team player who works well with cross-functional teams to achieve common goals.
An innovative thinker who continuously seeks to improve processes and methodologies.
The Team Youll Be A Part Of: You will be part of a highly skilled and motivated team of formal verification engineers.
Our team is dedicated to ensuring the highest quality standards for digital IPs through rigorous verification processes.
We are committed to continuous learning and innovation, leveraging the latest tools and methodologies to stay at the forefront of the industry.
Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs.
Our total rewards include both monetary and non-monetary offerings.
Your recruiter will provide more details about the salary range and benefits during the hiring process.
Show more Show less

Employment Type: Full Time, Permanent

Read full job description

Prepare for Engineering Manager roles with real interview advice

People are getting interviews at Synopsys through

(based on 54 Synopsys interviews)
Campus Placement
Job Portal
Referral
Company Website
Walkin
29%
24%
19%
13%
2%
13% candidates got the interview through other sources.
High Confidence
?
High Confidence means the data is based on a large number of responses received from the candidates.

What people at Synopsys are saying

Engineering Manager salary at Synopsys

reported by 5 employees with 10-15 years exp.
₹38 L/yr - ₹55 L/yr
20% more than the average Engineering Manager Salary in India
View more details

What Synopsys employees are saying about work life

based on 331 employees
89%
93%
73%
89%
Flexible timing
Monday to Friday
No travel
Day Shift
View more insights

Synopsys Benefits

Submitted by Company
Health & Wellness
Career Growth
Community & Belonging
Submitted by Employees
Work From Home
Health Insurance
Cafeteria
Team Outings
Free Food
Soft Skill Training +6 more
View more benefits

Compare Synopsys with

Cadence Design Systems

4.1
Compare

Mentor Graphics

4.0
Compare

Ansys Software Private Limited

3.9
Compare

Infineon Technologies

3.9
Compare

Xilinx

4.2
Compare

National Instruments

3.9
Compare

Texas Instruments

4.1
Compare

Microchip Technology

4.0
Compare

Maxim Integrated

4.4
Compare

Intel

4.3
Compare

Applied Materials

3.9
Compare

Molex

3.9
Compare

Micron Technology

3.7
Compare

Broadcom

3.3
Compare

Apar Industries

4.1
Compare

TDK India Private Limited

3.9
Compare

Tessolve Semiconductor

3.6
Compare

Carl Zeiss

3.7
Compare

Exicom

3.9
Compare

NXP Semiconductors

3.8
Compare

Similar Jobs for you

Senior Layout Engineer at Synopsys (India) Private Limited

Noida

3-8 Yrs

₹ 12-16 LPA

Ams Verification Engineer at ConnectPro Management Consultants Pvt Ltd.

7-14 Yrs

₹ 19-40 LPA

Digital Designer at Infineon Technologies Pvt Ltd

Bangalore / Bengaluru

5-8 Yrs

₹ 12-16 LPA

Memory Layout Design Engineer at Vhunt4U

Bangalore / Bengaluru, Singapore

4-8 Yrs

₹ 8-14 LPA

Analog Engineer at Intel Technology India Pvt Ltd

Bangalore / Bengaluru

10-14 Yrs

₹ 13-18 LPA

Physical Design Engineer at Juntran Technologies Pvt Ltd

3-5 Yrs

₹ 12-15 LPA

Ams Verification Engineer at Kaizen

Hyderabad / Secunderabad

6-12 Yrs

₹ 20-35 LPA

Analog Layout Engineer at Juntran Technologies Pvt Ltd

3-5 Yrs

₹ 12-15 LPA

IP Verification Engineer at Mempage

5-8 Yrs

₹ 12-25 LPA

Senior Staff Engineer at Synopsys (India) Private Limited

Noida

8-13 Yrs

₹ 13-18 LPA

Synopsys Bangalore / Bengaluru Office Location

View all
Bangalore Office
Synopsys (India) Private Limited "RMZ Infinity", Tower A , 3rd,4th & 5th Floors, Muncipal #3, Benniganahalli, Old Madras Road Bangalore - Karnataka, India Bangalore
560016

Senior FV Engineering Manager

5-9 Yrs

Bangalore / Bengaluru

16hr ago·via naukri.com

Technical / Product Publications, Staff Engineer

3-8 Yrs

Hyderabad / Secunderabad

16hr ago·via naukri.com

Accounting, staff

2-6 Yrs

Bangalore / Bengaluru

16hr ago·via naukri.com

Statt Design Verification Engineer

3-7 Yrs

Bangalore / Bengaluru

16hr ago·via naukri.com

Senior Staff Engineer Product Validation Engineer STA Primetime

4-8 Yrs

Bangalore / Bengaluru

16hr ago·via naukri.com

Test & Validation Engineer

3-6 Yrs

Bangalore / Bengaluru

16hr ago·via naukri.com

GenAI/ LLM Specialist

2-6 Yrs

Noida

16hr ago·via naukri.com

Technical Publications Specialist

4-8 Yrs

Bangalore / Bengaluru

16hr ago·via naukri.com

R&D Engineer GenAI

2-6 Yrs

Noida

16hr ago·via naukri.com

IP Verification Manager

5-10 Yrs

Pune

16hr ago·via naukri.com
write
Share an Interview