ASIC Digital Design, Sr Staff Engineer

You will be working on VLSI IP verification of controllers related to complex protocols. You will be part of the Solutions Group at our Bangalore Design Center, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Verification domain.

Job Responsibilities -

• Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/DSC/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/ USB/ MIPI
• Be an individual contributor in the Verification Tasks - Architect testbenches, coding of TE, debug, verification coverage improvement, etc
• Will contribute to technical review of TE Code of medium complexity.
• Will contribute to technical process and quality improvement to achieve high quality deliveries
• Will be expected to Solve complex/ abstract problems
• The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment.
• The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.
• May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers.
• The role offers ample scope to mentor junior engineers and interns and to enhance ones leadership skills.

Key Qualifications and Experience

• Must have BSEE/ MSEE in EE with 8 to 14 years of relevant experience in the following areas:
• Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc
• Knowledge of one or more of protocols: Ethernet/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/USB/ DDR/PCIe MIPI/DSC. Knowledge of Ethernet protocol will be plus.
• Hands on experience with creating detailed design of components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM, OVM
• Test Planning, Coverage Planning, Assertion Planning
• Hands on experience with System Verilog coding and Simulation tools; Deep Knowledge of OOPs Concepts
• Experience with Perforce or similar revision control environment
• Knowledge of Perl/Shell scripts.
• Exposure to quality processes in the context of IP design and verification is an added advantage
• In addition, the candidate should have good communication skills, will be a team player and will have good problem solving skills.