ASIC Digital Design, Staff Engineer

• We are looking at Senior Design engineers to work on design and development of RTL based IP Cores implementing complex protocols
• The candidate will be part of the Solutions Group at our Bangalore Design Center, India and will be responsible for implementing RTL based IPs which are used in end-customer applications such as server farms, AI/machine learning, automotive, etc The candidate will work with our internationally based team of architects/designers/other verification team members across multiple sites worldwide
• The position offers learning and growth opportunities
• This is a Senior Technical Individual Contributor role and offers challenges to work on technically challenging IP Cores

• Understand Standards / functional specifications for the product and write architecture / microarchitecture specifications

• Make architecture decisions on the design
• Implement RTL design and basic verification
• Work with the verification team to define the verification requirements
• Perform technical lead role

Key Qualifications

Must have BSEE in EE with 8+ years of relevant experience or MSEE with 7+ years of relevant experience in the following areas:

• Knowledge of one or more of protocols DDR/PCIE/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/ Ethernet/ USB/ MIPI
• Hands on experience with creating micro-architecture/ detailed design from Functional Specifications
• Hands on experience with Verilog/ System Verilog coding and Simulation tools
• Synthesis flow and static timing flows, Lint, CDC, Formal checking
• Prior experience with SVA and formal verification tools is an added advantage
• Knowledge of C/C++, TCL, Perl, Python is an added advantage
• Ability to work independently, precisely and to drive innovation
• Ability to extract detailed product requirements from high-level specification
• Good communication skills.
• Experience of working with Functional safety, ISO26262 , FMEDA is an added advantage