ASIC Digital Design, Staff Engineer

• Individual contributor will be responsible for architectural and RTL design of microprocessor IP, Optimize design for performance, speed, area and power.
• Work with multi-site core teams. Review and improve verification test suites.
• At minimum, a Bachelor s degree in engineering is required with
•  7+ years of digital design experience using Verilog. Strong background in RISC architectures is required. Working experience in RISC microprocessor IP design, programming at assembly and
•  C/C++ level, DSP skills, an understanding of multi-core architectures and development techniques are a plus. Experience with multi-site development is helpful

The successful candidate is expected to:

• Design embedded RISC microprocessor IP at architectural and RTL level
• Optimize design for performance, speed, area and power, Generate hardware benchmarks and analyse results
• Develop standalone Verilog testbenches to verify their module
• Debug design issues / bugs working closely with verification team
  Maintain our current processor product line and their derivative products
• Develop and maintain project plans. Work closely with program managers