Senior Design Verification Engineer - System Verilog (5-9 yrs)

Design Verification Engineer.

We're looking for a Design Verification Engineer to join our Hyderabad/Bangalore team.

Key Qualification :

- From given design specification, define TB Architecture & develop TB components.

- Be a technical contributor in the Verification Tasks - Verilog coding of test-benches, System Verilog, SV Assertions, Test cases, data checks, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM etc.

- Develop block level test to speed up IP verification.

- Work with verification team to debug and fix RTL issues.

- Ability to work/ Prior experience as a Technical Lead a team is a major plus.

Preferred Experience.

- Typically requires a minimum of 8+ years of IP/SOC Verification experience.

- Able to create test-plan & coverage plan with the specification provided.

- Knowledge in Serdes and interface technologies such as DDR, MIPI, PCIe, CXL, USB, Ethernet is a plus.

- Knowledge in PHY Verification is a plus.

- Third party VIP integration & usage is a plus.

- Experience in GLS verification & Power-aware simulation is plus.

- Be able to study the coverage metrics and improve them with definition of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/ product specs.

- Familiarity with scripting languages such as shell, Perl, Python etc.is highly desirable.

- Exposure to quality processes (QA) in the context of IP design and verification is an added advantage.

- Experience with Perforce, Git or similar revision control environment.

- Creates deliverables which do not require supervision by a Senior Technical Engineer.

- May need to interact with customers to discuss/ understand customers' specification requirements, if needed.

- Has strong desire to learn and explore new technologies.

- Demonstrates good analysis and problem-solving skills.