SmartSoc Solutions - Senior Physical Design Engineer - RTL Design (3-8 yrs)

Job Description :

Company Description :

SmartSoC Solutions is a leading Product Engineering Services company with expertise in Semiconductor Design Services, Embedded Systems, Digital Solutions, Artificial Intelligence, Machine Learning, IoT, Networking, and Robotics.

We serve industries like Semiconductor, Consumer Electronics, Telecom & Data Networking, Industrial, Automotive, and Agriculture.

Our global team of 1,250 scientists and engineers across multiple countries is dedicated to driving innovation and success for our clients.

Role Description :

This is a full-time on-site role for a Senior Physical Design Engineer based in Bengaluru. The Senior Physical Design Engineer will be responsible for tasks such as Physical Design, Physical Verification, Logic Design, Circuit Design, and RTL Design on a daily basis.

Qualifications :

- Physical Design, Physical Verification, and Logic Design skills.

- Circuit Design and RTL Design skills.

- Experience in implementing physical design flows.

- Strong understanding of semiconductor design methodologies.

- Ability to work effectively in a team environment.

- Bachelor's or Master's degree in Electrical Engineering or related field.

- Excellent problem-solving and analytical skills.

- Experience with EDA tools like Cadence or Synopsys.

Requirements :

- Senior Engineer, Technical Lead, and Architect levels

- Hands-on experience in handling block/chip level implementation from Netlist to GDSII

- Must possess hands on experience in timing closure and physical verification closure

- Experience in handling lower tech nodes that include 7nm, 10nm, 16nm, 28nm 40nm, etc.

- Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such ICC/ICC2, Fusion Compiler or Innovus

- Must have the ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time

- Must possess excellent scripting skills TCL or Perl or Python

- Experience in Synthesis and Formal is a plus

Responsibility :

- Participate at either the IP or SOC level with opportunity for change in focus as projects needs allow

- Partner with other engineers from the design team and other disciplines to define and develop ASIC physical designs.

- This would include physical designers from both SOC and IP Participate in defining flows, methods, select tools, drive continual improvement, and closure of issues Work with advanced process node technology